Inherent Fault-Tolerant Multilevel Inverter

Due to the many semiconductor switches used in power conversion, switch failures are more common in multilevel inverters (MLIs). Therefore, designing an MLI with fault-tolerant (FT) capability is of utmost importance for uninterrupted supply. This article demonstrates various fault scenarios and offers numerous switching strategies for the different fault combinations. The detailed analysis of the proposed topology in terms of single (FT1), double (FT2), triple (FT3), quadruple (FT4), and quintuple (FT5) switch failures has been discussed in detail. The proposed topology uses phase disposition sinusoidal pulse width modulation (PD-SPWM) for gate signal generation. Further, a brief comparison analysis of the proposed topology in terms of device count, total blocking voltage (TBV), pre-and post-fault voltage level, pre-and post-fault voltage magnitude for the various fault combinations have been performed and compared with the exact nature of the available topology. The reliability analysis of the proposed topology has also been done mathematically. The simulation study of the proposed topology has been carried out in the MATLAB/SIMULINK environment for all possible switch fault combinations, and real-time validation is also done in OPAL-RT 4510.