<p>This work presents an ultra-low-energy and high-speed silicon neuron based on a high-k dual-gate tunnel field effect transistor (HDG-TFET). Through 2-D TCAD simulations, HDG-TFET effectively emulates a leaky-integrate-and-fire (LIF) neuron by leveraging impact ionization mechanisms. The proposed neuron exhibits an energy consumption of 615 aJ per spike—orders of magnitude lower than existing silicon-based implementations,i.e.,   5.69 <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="12668_2025_2047_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">$\times $</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> 10<InlineEquation ID="IEq2"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="12668_2025_2047_Article_IEq2.gif" Format="GIF" Height="10" Rendition="HTML" Resolution="72" Type="Linedraw" Width="8" /> </InlineMediaObject> <EquationSource Format="TEX">$^{4}$</EquationSource> <EquationSource Format="MATHML"><math> <mmultiscripts> <mrow /> <mrow /> <mn>4</mn> </mmultiscripts> </math></EquationSource> </InlineEquation>, 7.32 <InlineEquation ID="IEq3"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="12668_2025_2047_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">$\times $</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> 10 <InlineEquation ID="IEq4"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="12668_2025_2047_Article_IEq2.gif" Format="GIF" Height="10" Rendition="HTML" Resolution="72" Type="Linedraw" Width="8" /> </InlineMediaObject> <EquationSource Format="TEX">$^{4}$</EquationSource> <EquationSource Format="MATHML"><math> <mmultiscripts> <mrow /> <mrow /> <mn>4</mn> </mmultiscripts> </math></EquationSource> </InlineEquation>,   9235,  406,  10.2,  293, and  1853 times less than the SOI CMOS, Single MOSFET, Biristor, feedback FET (FBFET), bulk FinFET, L shaped-BIMOS, and DG-JLFET, respectively. Additionally, the reported device has the threshold voltage of <InlineEquation ID="IEq5"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="12668_2025_2047_Article_IEq5.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">$-$</EquationSource> <EquationSource Format="MATHML"><math> <mo>-</mo> </math></EquationSource> </InlineEquation>0.342 V and achieves a spiking frequency of approximately 10 GHz, significantly surpassing conventional neuromorphic designs. The HDG-TFET structure eliminates the need for a floating body to store excess carriers, facilitating device scalability and energy efficiency. These findings position HDG-TFET as a promising candidate for next-generation neuromorphic hardware, offering a path toward large-scale, ultra-efficient spiking neural network (SNN) implementations.</p>

Neuromorphic Computing Based on Tunnel FET-LIF Neuron with Plausible Mimicking Efficiency

期刊论文
发表日期：

2025年6月25日

查看全文

Priyanka,
Sangeeta Singh,
Meena Panchore

摘要

This work presents an ultra-low-energy and high-speed silicon neuron based on a high-k dual-gate tunnel field effect transistor (HDG-TFET). Through 2-D TCAD simulations, HDG-TFET effectively emulates a leaky-integrate-and-fire (LIF) neuron by leveraging impact ionization mechanisms. The proposed neuron exhibits an energy consumption of 615 aJ per spike—orders of magnitude lower than existing silicon-based implementations,i.e., 5.69 $\times $ $\times$ 10 $^{4}$ $^{4}$ , 7.32 $\times $ $\times$ 10 $^{4}$ $^{4}$ , 9235, 406, 10.2, 293, and 1853 times less than the SOI CMOS, Single MOSFET, Biristor, feedback FET (FBFET), bulk FinFET, L shaped-BIMOS, and DG-JLFET, respectively. Additionally, the reported device has the threshold voltage of $-$ $-$ 0.342 V and achieves a spiking frequency of approximately 10 GHz, significantly surpassing conventional neuromorphic designs. The HDG-TFET structure eliminates the need for a floating body to store excess carriers, facilitating device scalability and energy efficiency. These findings position HDG-TFET as a promising candidate for next-generation neuromorphic hardware, offering a path toward large-scale, ultra-efficient spiking neural network (SNN) implementations.