Building on the p-n junction gate DRAM structure presented in [1], this paper evaluates its potential as a synaptic element for neuromorphic computing. Unlike conventional floating-body-based one-transistor dynamic random-access memory (1T-DRAM) [2–4], the proposed device utilizes a p-type gate to store holes, enabling a non-destructive and stable read mechanism while preserving the advantages of fast operation and compact integration. Potentiation and depression operations are realized through band-to-band tunneling (BTBT) by biasing the gate and drain terminals. To address the abrupt conductance drop typically observed in early depression pulses, a partial Incremental Step Pulse Programming (ISPP) scheme is introduced, significantly improving the linearity and controllability of the weight-downdating process. Device-level performance was further benchmarked using fitted conductance curves in NeuroSim V3.0, where the ISPP based implementation achieved a peak inference accuracy of 85.01%, outperforming the general case with improved consistency. These results demonstrate the proposed device’s potential as a scalable and reliable synaptic element for future neuromorphic hardware platforms that require multilevel weight modulation and read stability.
