This work investigates triple-metal (TM) gate work-function engineering applied to both junctionless (JL) and inversion-mode (IM) double surrounding gate (DSG) germanium (Ge) nanotube (NT) MOSFETs for sub-3-nm technology nodes. A comprehensive analysis of DC and analog/RF performance metrics is performed, including drain current (ID), transconductance (gm), transconductance gain factor (TGF), cutoff frequency (fT), transconductance frequency product (FTP), intrinsic time constant (τ), and total series resistance (RSD+CH), for a gate length of 3 nm, using Silvaco ATLAS 3D TCAD. Carrier transport is modeled using the Non-Equilibrium Green’s Function (NEGF) formalism, self-consistently coupled with the Schrödinger and Poisson equations. The IM Ge NT device employs a lightly doped channel, Al2O3 gate dielectric with a thickness of 0.8 nm, and a Ge nanotube channel radius of 1.5 nm. A detailed comparison between IM and JL TM-DSG GeNT MOSFETs is presented. To ensure a fair comparison, the doping concentration of the JL GeNT is optimized under two conditions: (i) matching the ON-state current (ION) of the IM device and (ii) achieving an identical threshold voltage (VTH). The results demonstrate that the OFF-state current (IOFF) of the JL device is approximately 15.81 times and 11.67 times lower than that of the IM device under matched ION and VTH conditions, respectively. Consequently, the ION/IOFF ratio of the JL device improves by 15.78 times and 12.52 times, respectively. Furthermore, the JL GeNT MOSFET exhibits a low drain-induced barrier lowering (DIBL) of ~ 30.88 mV/V, a near-ideal subthreshold slope of 60 mV/dec, and a high ION/IOFF ratio of approximately <InlineEquation ID="IEq1"> <EquationSource Format="TEX">$3.82\times {10}^{11}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>3.82</mn> <mo>×</mo> <msup> <mrow> <mn>10</mn> </mrow> <mn>11</mn> </msup> </mrow> </math></EquationSource> </InlineEquation>. In addition, enhanced gm, TGF, fT, and FTP, along with reduced τ and RSD+CH, are achieved compared to reported cylindrical gate-all-around (CGAA) MOSFETs in existing literature.

Triple Metal Gate Work Function Engineering to Enhance DC and Analog/RF Parameters of Junctionless Double Surrounding Gate Ge Nanotube MOSFET with High-κ Dielectric for the Upcoming Sub 3 nm Technology Node

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发表日期：

2026年7月29日

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Sanjay,
Vibhor Kumar,
Anil Vohra

摘要

This work investigates triple-metal (TM) gate work-function engineering applied to both junctionless (JL) and inversion-mode (IM) double surrounding gate (DSG) germanium (Ge) nanotube (NT) MOSFETs for sub-3-nm technology nodes. A comprehensive analysis of DC and analog/RF performance metrics is performed, including drain current (I_D), transconductance (g_m), transconductance gain factor (TGF), cutoff frequency (f_T), transconductance frequency product (FTP), intrinsic time constant (τ), and total series resistance (R_SD+CH), for a gate length of 3 nm, using Silvaco ATLAS 3D TCAD. Carrier transport is modeled using the Non-Equilibrium Green’s Function (NEGF) formalism, self-consistently coupled with the Schrödinger and Poisson equations. The IM Ge NT device employs a lightly doped channel, Al₂O₃ gate dielectric with a thickness of 0.8 nm, and a Ge nanotube channel radius of 1.5 nm. A detailed comparison between IM and JL TM-DSG GeNT MOSFETs is presented. To ensure a fair comparison, the doping concentration of the JL GeNT is optimized under two conditions: (i) matching the ON-state current (I_ON) of the IM device and (ii) achieving an identical threshold voltage (V_TH). The results demonstrate that the OFF-state current (I_OFF) of the JL device is approximately 15.81 times and 11.67 times lower than that of the IM device under matched I_ON and V_TH conditions, respectively. Consequently, the I_ON/I_OFF ratio of the JL device improves by 15.78 times and 12.52 times, respectively. Furthermore, the JL GeNT MOSFET exhibits a low drain-induced barrier lowering (DIBL) of ~ 30.88 mV/V, a near-ideal subthreshold slope of 60 mV/dec, and a high I_ON/I_OFF ratio of approximately $3.82\times {10}^{11}$ $3.82 \times 10^{11}$ . In addition, enhanced g_m, TGF, f_T, and FTP, along with reduced τ and R_SD+CH, are achieved compared to reported cylindrical gate-all-around (CGAA) MOSFETs in existing literature.