<p>Thermal noise plays a pivotal role in determining the high-frequency behavior and reliability of nanoscale transistors, particularly Gate-All-Around (GAA) nanowire MOSFETs. At such dimensions, this noise arises from intrinsic temperature-induced carrier fluctuations and structural imperfections, significantly impacting signal integrity. A common fabrication challenge at the nanoscale is achieving ideal geometries; deviations such as trapezoidal cross-sections with inclined sidewalls are frequently observed due to etching limitations. In this work, we examine how variations in sidewall inclination affect the thermal noise behavior of GAA nanowire transistors. Using thermally-aware simulation techniques, we systematically analyze the impact of sidewall angles (up to 20°) on key noise parameters, including channel thermal noise, induced gate noise, and gate-channel noise correlation. In addition, the sidewall inclination's effect along with the thermal contact resistance (R_tc) on thermal noise is explored. All the simulations have been carried out using the Sentaurus device simulator.</p>