This paper presents a Stepped-Gate with Bottom-side Super Junction Vertical Double-Diffused MOSFET (SG-BSJ VDMOS), that applies gate engineering across both the channel and drift regions, and features a super-junction layer positioned near the drain area on the bottom side of the drift region. The device architecture comprises three gate segments arranged in a stepped configuration. The first, near the source, uses P \(^+\) polysilicon with a thin oxide layer for efficient channel charge control. The second and third gates utilize N \(^+\) polysilicon, with the third gate positioned over the drift region and designed with a thicker oxide to reduce the gate-to-drain charge density. Due to the effect of gate engineering, the area-specific on-resistance diminished. Furthermore, a super-junction concept enhances breakdown voltage. Simulation results using the Silvaco ATLAS TCAD tool show that these design enhancements significantly improve peak transconductance, gate charge, on-resistance ( \(\text {R}_{\text {on}}\) ), and breakdown voltage ( \(\text {BV}_{\text {DS}}\) ). The simulation results validate that the proposed SG-BSJ VDMOS device structure enhances the breakdown voltage from 278.7 V to 539.75 V, representing an improvement of 93.3%. Furthermore, the figure of merit (FOM) increases from 2.65 \({MWcm^{-2}}\) to 10.38 \({MWcm^{-2}}\) , achieving an improvement of 291.64%. The combined use of stepped-gate (SG) engineering and the super-junction (SJ) concept mitigates the tradeoff between on-resistance and breakdown voltage, improving the device’s FOM.
