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<p>During vertical channel 3D NAND fabrication, plasma-induced damage creates surface defects, which lead to the formation of voids at different locations of the subsequently grown epi-plug. The void's location, especially near the edge of the substrate-epi plug, as well as in the side wall of the epi-plug, is more critical. The void at the edge of the substrate-epi plug increases V<sub>th</sub>, SS, and R<sub>ch</sub> and reduces I<sub>on</sub>, compared to no void. Voids along the sidewall of the epi-plug also significantly affect electrical performance. Further trap formation around the void degrades performance, increasing V<sub>th</sub>, SS, and R<sub>ch</sub> while significantly reducing I<sub>on</sub> compared to without trap. Traps around voids far from the GSL (Ground Select Line) similarly degrade performance as those near the GSL and epi-plug edge. We also investigated the effects of voids during program/erase characteristics. Our study emphasizes how the geometric location of voids and the distribution of surrounding traps influence the reliability and electrical performance of 3D NAND devices.</p>

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Investigation of EPI Plug Voids Impacts on Electrical Performance of 3D NAND

  • 期刊论文

  • 发表日期：

    2025年12月9日

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  • Dibyadrasta Sahoo,
  • Ankit Gaurav,
  • Mohd Ashraf Lone,
  • Sanjeev Kumar Manhas

摘要

During vertical channel 3D NAND fabrication, plasma-induced damage creates surface defects, which lead to the formation of voids at different locations of the subsequently grown epi-plug. The void's location, especially near the edge of the substrate-epi plug, as well as in the side wall of the epi-plug, is more critical. The void at the edge of the substrate-epi plug increases Vth, SS, and Rch and reduces Ion, compared to no void. Voids along the sidewall of the epi-plug also significantly affect electrical performance. Further trap formation around the void degrades performance, increasing Vth, SS, and Rch while significantly reducing Ion compared to without trap. Traps around voids far from the GSL (Ground Select Line) similarly degrade performance as those near the GSL and epi-plug edge. We also investigated the effects of voids during program/erase characteristics. Our study emphasizes how the geometric location of voids and the distribution of surrounding traps influence the reliability and electrical performance of 3D NAND devices.