Quadruple Metal Gate Work Function Engineering to Enhance DC and Analog/RF Performance in Junctionless Cylindrical GAA Si Nanowire MOSFET at Sub 3 nm Technology Node
摘要
This study investigates the DC and RF characteristics of Quadruple Metal (QM) Inversion Mode (IM) and Junctionless (JL) Cylindrical Gate-All-Around (CGAA) Silicon Nanowire (SiNW) MOSFETs with a 3 nm gate length, using Silvaco ATLAS 3D TCAD and the Non-Equilibrium Green Function (NEGF) method with self-consistent Schrödinger-Poisson solutions. Key parameters analyzed include drain current (ID), transconductance (gm), transconductance generation factor (TGF), cut-off frequency (fT), frequency transconductance product (FTP), transit time (τ), and total resistance (RSD+CH) for a SiNW with a 3 nm diameter and 0.8 nm gate oxide. The impact of QM gate work function engineering is compared between IMQM and JLQM devices. JL devices are optimized for equivalent ION and VTH as IM devices, achieving ~ 246.96 times and ~ 86.32 times lower IOFF, respectively. QM gate variation reduces DIBL in both devices, with JL SiNW showing superior performance: DIBL (~ 75.42 mV/V), near-ideal subthreshold swing (~ 60 mV/dec), and high ION/IOFF (~ 1.92 × 1011), outperforming IM devices in SS, DIBL, ION/IOFF, gm, TGF, fT, τ, FTP, and RSD+CH.