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<p>An abrupt tunnelling intersection needs to exist for a TFET (tunnel field effect transistor) to operate with outstanding electronic and switching capabilities. Additionally, reliability challenges resulting from trap charges created during TFET manufacturing need to be addressed for TFET design. This study examines the dependability of the suggested DGO (dual gate oxide) Tunnel FET centred around bilateral tunnelling (BT-TFET) incorporating low work-function metal strip (LWMS) for the first time. Sharp tunnelling interface at the channel and source conjunction is generated by administering LWMS in the dielectric with&#xa0;high-<i>k</i> region near the source, thereby benefitting threshold voltage (<i>V</i><sub><i>th</i></sub>) and subthreshold swing (<i>SS</i>). Furthermore, the gate dielectric's dual oxide promotes the capacitance interaction involving the gate and the dielectric, strengthening the device's quality and dependability features. The recommended LWMS-DGO-BT-TFET demonstrates a diminished<i> V</i><sub><i>th</i></sub> of 0.6&#xa0;V, a superior ON to OFF state current proportion of 10<sup>13</sup>, and a dropped <i>SS</i> of 14.7&#xa0;mV/decade. The dependability of the suggested device has been investigated by assessing the repercussions of positive as well as negative traps on various metrics such as static or DC, RF/analogue performance statistics, consisting of electric field, transfer metrics, transconductance (<i>g</i><sub><i>m</i></sub>), and so forth, of the suggested LWMS-DGO-BT-TFET and the original single gate oxide bilateral tunnelling TFET incorporating LWMS (LWMS-SGO-BT-TFET). Beyond that, contrasting evaluation of both of these designs&#xa0;was additionally conducted with respect to distortion statistics comprising third-order voltage intercept point (<i>VIP</i><sub><i>3</i></sub>),&#xa0;second-order and third-order&#xa0;transconductance coefficients. Research has shown that positive traps lift the ON-current of the&#xa0;suggested design&#xa0;by 7.38% and the LWMS-SGO-BT-TFET&#xa0;by 48.90%. Whereas, negative ITCs prompt&#xa0;the ON-current of the suggested design&#xa0;and the classical design&#xa0;to decline by 8.87% and 29.34%, correspondingly. Accordingly, the study found that LWMS-DGO-BT-TFET, which features multiple traps, is more resilient to performance volatility than both DGO-BT-TFET, which is a typical device, and LWMS-SGO-BT-TFET, which is a classical device.</p>

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Design and Performance Analysis of New Metal Strip Incorporated Dual Oxide Dual Tunnel FET Evaluating Trap Charges for Augmented Reliability

  • 期刊论文

  • 发表日期：

    2025年10月10日

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  • Priyanka Kwatra,
  • Sajai Vir Singh,
  • Kaushal Nigam

摘要

An abrupt tunnelling intersection needs to exist for a TFET (tunnel field effect transistor) to operate with outstanding electronic and switching capabilities. Additionally, reliability challenges resulting from trap charges created during TFET manufacturing need to be addressed for TFET design. This study examines the dependability of the suggested DGO (dual gate oxide) Tunnel FET centred around bilateral tunnelling (BT-TFET) incorporating low work-function metal strip (LWMS) for the first time. Sharp tunnelling interface at the channel and source conjunction is generated by administering LWMS in the dielectric with high-k region near the source, thereby benefitting threshold voltage (Vth) and subthreshold swing (SS). Furthermore, the gate dielectric's dual oxide promotes the capacitance interaction involving the gate and the dielectric, strengthening the device's quality and dependability features. The recommended LWMS-DGO-BT-TFET demonstrates a diminished Vth of 0.6 V, a superior ON to OFF state current proportion of 1013, and a dropped SS of 14.7 mV/decade. The dependability of the suggested device has been investigated by assessing the repercussions of positive as well as negative traps on various metrics such as static or DC, RF/analogue performance statistics, consisting of electric field, transfer metrics, transconductance (gm), and so forth, of the suggested LWMS-DGO-BT-TFET and the original single gate oxide bilateral tunnelling TFET incorporating LWMS (LWMS-SGO-BT-TFET). Beyond that, contrasting evaluation of both of these designs was additionally conducted with respect to distortion statistics comprising third-order voltage intercept point (VIP3), second-order and third-order transconductance coefficients. Research has shown that positive traps lift the ON-current of the suggested design by 7.38% and the LWMS-SGO-BT-TFET by 48.90%. Whereas, negative ITCs prompt the ON-current of the suggested design and the classical design to decline by 8.87% and 29.34%, correspondingly. Accordingly, the study found that LWMS-DGO-BT-TFET, which features multiple traps, is more resilient to performance volatility than both DGO-BT-TFET, which is a typical device, and LWMS-SGO-BT-TFET, which is a classical device.