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<p>Recently introduced nanosheet field-effect transistors (NS FETs) are cutting-edge technology in the foundry business. Compared to conventional FinFETs, NS FETs exhibit superior gate controllability and output current. However, NS FETs are still limited by the presence of a substrate parasitic n-type metal–oxide–semiconductor (NMOS), which increases off-state current (<i>I</i><sub>OFF</sub>) and impacts overall device reliability. Trench gate (TG) NS FETs have been proposed as a solution, but the process for source/drain (S/D) formation in TG NS FETs remains unclear. This study focuses on optimizing the junction depth (<i>X</i><sub>j</sub>) in TG NS FETs, which is a key factor to enhancing device performance. A shallow <i>X</i><sub>j</sub> increases the effective gate length (<i>L</i><sub>G.EFF</sub>) of the substrate parasitic NMOS, effectively suppressing short-channel effects (SCEs). To guide the development of these TG NS FETs, both device fabrication and electrical characteristics were simulated using 3-dimensional (3-D) technology computer-aided design (TCAD), with various design parameters considered.</p>

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Junction Depth Optimization in Trench Gate Nanosheet FETs for Reduced Off-State Current

  • 期刊论文

  • 发表日期：

    2025年8月12日

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  • Da-Eun Bang,
  • Moon-Kwon Lee,
  • Eui-Cheol Yun,
  • Tae-Hyun Kil,
  • Hyo-Jun Park,
  • Ju-Won Yeon,
  • Min-Woo Kim,
  • Su-Jin Jeon,
  • A-Young Kim,
  • Jun-Young Park

摘要

Recently introduced nanosheet field-effect transistors (NS FETs) are cutting-edge technology in the foundry business. Compared to conventional FinFETs, NS FETs exhibit superior gate controllability and output current. However, NS FETs are still limited by the presence of a substrate parasitic n-type metal–oxide–semiconductor (NMOS), which increases off-state current (IOFF) and impacts overall device reliability. Trench gate (TG) NS FETs have been proposed as a solution, but the process for source/drain (S/D) formation in TG NS FETs remains unclear. This study focuses on optimizing the junction depth (Xj) in TG NS FETs, which is a key factor to enhancing device performance. A shallow Xj increases the effective gate length (LG.EFF) of the substrate parasitic NMOS, effectively suppressing short-channel effects (SCEs). To guide the development of these TG NS FETs, both device fabrication and electrical characteristics were simulated using 3-dimensional (3-D) technology computer-aided design (TCAD), with various design parameters considered.