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<p>In this paper, a novel structure, double gate with inverted T-shaped TFET (DG-IT-TFET has been proposed and studied with and without charge plasma technique. We have further studied the DG-IT-TFET structures on three different substrate namely, Silicon-based, Germanium-based and hetero Silicon–Germanium based. In this novel structure we have used 15&#xa0;nm gate thickness for both gates. Lateral length (L<sub>T</sub>) has been optimized as 1&#xa0;nm that gives vertical tunneling and enhanced the subthreshold slope (SS). The novel structure with dual gate provides flexibility over electrostatics control, improved ON current, lowers subthreshold swing and improves ON-current to OFF-current ratio. One has also studied and analyzes the digital and analog parameters of novel structure DG-IT-TFET with and without charge plasma. In this charge plasma concept, apply appropriate work function to both electrodes. Our comparative study shows that Si-DG-IT-TFET(without charge plasma) structure has most significant improvement in ON current of value 2.2 × 10<sup>−4</sup>A/μm, very low leakage current 6.8 × 10<sup>−17</sup>A/μm, and very low SS with a value of (13.5&#xa0;mV/dec). Si-DG-IT-TFET structure produces improved I<sub>ON</sub>/I<sub>OFF</sub> with the peak value of 10<sup>12</sup>. Comparative results with charge plasma and without charge plasma of DG-IT-TFET structure listed are Tables 2 and 3. The Ge based DG-IT-TFET(without charge plasma) structure shows promising results for analog circuits. Thus our proposed DG-IT-TFET structure is good electrical characteristics. Thus this structure is most promising candidate for extremely low power digital and analog chips.</p>

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Comparative Study of Double Gate Inverted-T Shaped, TFET for Extremely Low Power Logic and Analog Circuit in AI Chips

  • 期刊论文

  • 发表日期：

    2025年8月13日

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  • Saket Suman,
  • A. Srivastava,
  • Angsuman Sarkar

摘要

In this paper, a novel structure, double gate with inverted T-shaped TFET (DG-IT-TFET has been proposed and studied with and without charge plasma technique. We have further studied the DG-IT-TFET structures on three different substrate namely, Silicon-based, Germanium-based and hetero Silicon–Germanium based. In this novel structure we have used 15 nm gate thickness for both gates. Lateral length (LT) has been optimized as 1 nm that gives vertical tunneling and enhanced the subthreshold slope (SS). The novel structure with dual gate provides flexibility over electrostatics control, improved ON current, lowers subthreshold swing and improves ON-current to OFF-current ratio. One has also studied and analyzes the digital and analog parameters of novel structure DG-IT-TFET with and without charge plasma. In this charge plasma concept, apply appropriate work function to both electrodes. Our comparative study shows that Si-DG-IT-TFET(without charge plasma) structure has most significant improvement in ON current of value 2.2 × 10−4A/μm, very low leakage current 6.8 × 10−17A/μm, and very low SS with a value of (13.5 mV/dec). Si-DG-IT-TFET structure produces improved ION/IOFF with the peak value of 1012. Comparative results with charge plasma and without charge plasma of DG-IT-TFET structure listed are Tables 2 and 3. The Ge based DG-IT-TFET(without charge plasma) structure shows promising results for analog circuits. Thus our proposed DG-IT-TFET structure is good electrical characteristics. Thus this structure is most promising candidate for extremely low power digital and analog chips.