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<p>In this work, Triple Metal (TM) and Quadruple Metal (QM) gate engineering have been done for both junctionless (JL) inversion mode (IM) and Double surrounding Gate (DSG) Si nanotube (SiNT) MOSFET to study drain current (I<sub>D</sub>) characteristics for gate length of 2&#xa0;nm using Silvaco ATLAS 3D TCAD. For this, the Non Equilibrium Green’s Function (NEGF) method has been used along with self-consistent solution of Schrödinger’s equation with Poisson’s equation. In case of IM channel region of SiNT device, there is lightly doping. In this device SiO<sub>2</sub> is used as gate oxide thickness of 0.8&#xa0;nm, with Si channel radius of 1.5&#xa0;nm have been used. A comparison has also been done between results of TM DSG and QM DSG SiNT. For a reasonable comparison between JL and IM SiNT, in each case of TM and QM JL SiNT doping concentration are optimized for two goals (i) to obtain the same I<sub>ON</sub> as IM SiNT and (ii) to obtain the same threshold voltage (V<sub>TH</sub>) as IM SiNT. This results in about 10 times smaller I<sub>OFF</sub> for both JL, I<sub>ON</sub> and V<sub>TH</sub> matching SiNT for both TM and QM case. This also results in about 10 times higher I<sub>ON</sub>/I<sub>OFF</sub> current ratio for all JL device as compared to IM device for both TM and QM case. All used JL SiNT results in smaller DIBL in both TM and QM case as compared to IM SiNT device. In this work for JL SiNT, a smaller DIBL ~ 36.46&#xa0;mV/V, nearly ideal subthreshold slope (SS) ~ 60&#xa0;mV/dec, and higher I<sub>ON</sub>/I<sub>OFF</sub> current ratio ~ 4.41 × 10<sup>10</sup> have been obtained in comparison to available literature CGAA device results.</p>

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Performance Evaluation of Junctionless Double Surrounding Gate Si Nanotube MOSFET Using Triple and Quadruple Metal Gate Work Function Engineering for the Upcoming Sub 2 nm Technology Node

  • 期刊论文

  • 发表日期：

    2025年4月4日

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  • Sanjay,
  • Vibhor Kumar,
  • Anil Vohra

摘要

In this work, Triple Metal (TM) and Quadruple Metal (QM) gate engineering have been done for both junctionless (JL) inversion mode (IM) and Double surrounding Gate (DSG) Si nanotube (SiNT) MOSFET to study drain current (ID) characteristics for gate length of 2 nm using Silvaco ATLAS 3D TCAD. For this, the Non Equilibrium Green’s Function (NEGF) method has been used along with self-consistent solution of Schrödinger’s equation with Poisson’s equation. In case of IM channel region of SiNT device, there is lightly doping. In this device SiO2 is used as gate oxide thickness of 0.8 nm, with Si channel radius of 1.5 nm have been used. A comparison has also been done between results of TM DSG and QM DSG SiNT. For a reasonable comparison between JL and IM SiNT, in each case of TM and QM JL SiNT doping concentration are optimized for two goals (i) to obtain the same ION as IM SiNT and (ii) to obtain the same threshold voltage (VTH) as IM SiNT. This results in about 10 times smaller IOFF for both JL, ION and VTH matching SiNT for both TM and QM case. This also results in about 10 times higher ION/IOFF current ratio for all JL device as compared to IM device for both TM and QM case. All used JL SiNT results in smaller DIBL in both TM and QM case as compared to IM SiNT device. In this work for JL SiNT, a smaller DIBL ~ 36.46 mV/V, nearly ideal subthreshold slope (SS) ~ 60 mV/dec, and higher ION/IOFF current ratio ~ 4.41 × 1010 have been obtained in comparison to available literature CGAA device results.