Demonstration and Performance Assessment of Dopant Free TFET Including Lattice Heating and Temperature Effects

The failure of MOSFET at ultra-small dimensions has directed researchers to investigate alternate FETs. Vast applications and the compactness of integrated circuits have made the investigation of FETs against variation in temperature and lattice heating very crucial; hence, in this work, the effect of variation in temperature and lattice heating on the characteristics of a charge plasma based tunnel field-effect transistor is analyzed. To enhance tunnelling probability, SiGe composite is used at the source electrode, and silicon is used across the drain terminal. To overcome the fabrication issues faced by doped TFET, charge plasma technique is utilised to create a doping profile. Variation is examined on different device, analog and linearity parameters. For investigation, temperature is varied from 200 to 400 K, and it was detected that operation at a lower temperature results in better I_ON/I_OFF characteristics but degrades the linearity characteristics of the device. At 200 K, lowest I_OFF of order 10-19A/µm and high I_ON/I_OFF of 4.66 × 1012 is obtained. Work done also illustrates that the effect of lattice heating becomes dominant at voltages greater than 1.5 V. Lattice hating improves analog characteristics by a factor of 1.02 but degrades linearity parameters such as VIP3 and IIP3 by 0.27dBm and 0.03dBm respectively.