The Effect of a Dual Oxide - Dual Gate Material and a Sensitivity Analysis on the Performance of a Junctionless Tunnel FET

In this manuscript, we present a innovative idea that utilizes dual oxide materials and multiple gates in the design of the junctionless tunnel field effect transistor (DO-DMG-JL-TFET). This idea can be used to increase the JL-TFET’s efficiency. The proposed design has dual oxide materials, specifically a low-K dielectric on the drain side and a high-K dielectric on the source side. This configuration will enhance the capacitive coupling between the gate and substrate. Conversely, the control gate has been split into two sections, with the implementation of work-function mechanisms to enhance the device characteristics with regard to DC and analog/radio-frequency. Both the oxide layer and control gate are positioned on the N \(^{+}\) ${}^{+}$ type doped silicon substrate to create a Tunnel Field Effect Transistor (TFET) with similar doping as typical TFETs. This is done to simplify the fabrication process. Upon successfully modeling the proposed device, we conducted a comparison study and determined that the proposed concept significantly contributed to the enhancement of the ON state current (I \(_{on}\) ${}_{\mathit{on}}$ ), threshold voltage (V \(_{th}\) ${}_{\mathit{th}}$ ), switching ratio (I \(_{on}\) ${}_{\mathit{on}}$ /I \(_{off}\) ${}_{\mathit{off}}$ ), and subthreshold swing (SS). Furthermore, we have also assessed the influence of temperature on the proposed device in relation to DC and analog/radio frequency (RF). The simulations were conducted using the SILVACO ATLAS technology computer-aided design (TCAD) simulator. Therefore, this research indicates that the proposed device (DO-DMG-JL-TFET) is suitable for ultra-low power, high-frequency, and high temperature applications.