Design Transmission Gates Using Double-Gate Junctionless TFETs

Transmission gate has been implemented using tunnel field-effect-transistor (TFET) in the presented work. This work demonstrates the benefits of replacing MOS devices with TFET from conventional CMOS circuits for low-power sub-micron technology. TFET with few structural modifications is described as a worthy contender for the MOSFETs. As an illustration to it the transmission gate block, which is one of the popular logic styles, is implemented using modified junction less TFETs with P + pocket near the source end. In this work, firstly, a single gate TFET with buried SOI followed by double gate (DG) TFETs is demonstrated for implementation of the transmission gate (TG). Both the devices have junction less structure with a p + pocket or n + pocket region in n-JL TFET or p-JL TFET respectively towards source. The major parameter of evaluation is voltage transfer characteristics, output characteristics and device ON and OFF current for obtaining standard ON/OFF current ratio in low-power logic circuit implementations. The fabrication steps of both devices are also depicted with the help of projected lithographic processes. The device implementation and simulation are carried out on the Cogenda Visual TCAD tool at a 20 nm technology node.