A new Vertical C-shaped Silicon Channel Nanosheet FET with Stacked High-K Dielectrics for Low Power Applications

Vertical Nanosheet Transistors serves as a potential substitute for the Nanowire and FinFET architecture at advanced technology nodes on account of higher drive current and superior control of short channel effects. In this article, a novel analysis of various stacked high-K dielectrics in n-type Vertical C-shaped Silicon Channel Nanosheet Field Effect Transistor (nVCNFET) is implemented. In-depth analysis is done on the effects of stacked high-K dielectrics on nVCNFET device performance and short channel effects. The nVCNFET with optimized gate oxide stack of Al₂O₃-TiO₂ exhibits a remarkable current ratio of 3.2 × 10¹⁶, which is 10⁷ times efficient over the reported Vertical Nanosheet FETs (NSFET) up to date. The Device performance and scaling compatibility of nVCNFET for sub-10 nm and 5 nm technology nodes are demonstrated to certify the device’s reliability. On the contrary, the proposed nVCNFET maintains ideal Subthreshold Swing (< 60 mV/decade) and yields 60% lesser DIBL value (8 mV/V) over the other Silicon-NSFETs. This concludes nVCNFET, a befitting candidate for low power and Dynamic Random Access Memory (DRAM) applications.