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<p>The main challenge in building all-optical computers is the size of the components in the arithmetic logic unit (ALU), which include optical logic gates, combinational circuits, and sequential circuits. Plasmonic devices, which address issues related to size and the diffraction limit in photonic devices, can overcome this problem. This paper proposes a new architecture for sequential logic gates that employs a plasmonic multi-layer structure with nanoscale dimensions to mimic the functions of D, T, and JK flip-flops with two outputs. Finite Element Method (FEM), which integrates D, T, and JK flip-flops on the same structure, is used to simulate the planned nanoscale design. We assume a transmission threshold of 0.5 at the resonance wavelength of 1550&#xa0;nm. Six critical performance parameters were evaluated, including optical transmittance, contrast ratio, and insertion losses. The results showed exceptional performance, with the JK flip-flop achieving a transmittance over 3.067 in one operating condition with a nearly optimal (MD) of 92.8%. All components exhibited very low IL (-1.35 to -0.96 dB) despite their tiny size (250 × 410&#xa0;nm²). The proposed design is crucial for photonic circuits and nanocircuits, especially for all-optical communication systems. These transmittances are attributed to the multiple inputs in the recommended designs. The suggested plasmonic flip-flop is simulated using the finite element approach in COMSOL Multiphysics.</p>

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Plasmonic D, T, and JK flip-flop based on nanoring resonator

  • 期刊论文

  • 发表日期：

    2026年5月3日

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  • Hassanen Alhakkak,
  • Saeed Golmohammadi,
  • Hamed Baghban,
  • Hadi Soofi

摘要

The main challenge in building all-optical computers is the size of the components in the arithmetic logic unit (ALU), which include optical logic gates, combinational circuits, and sequential circuits. Plasmonic devices, which address issues related to size and the diffraction limit in photonic devices, can overcome this problem. This paper proposes a new architecture for sequential logic gates that employs a plasmonic multi-layer structure with nanoscale dimensions to mimic the functions of D, T, and JK flip-flops with two outputs. Finite Element Method (FEM), which integrates D, T, and JK flip-flops on the same structure, is used to simulate the planned nanoscale design. We assume a transmission threshold of 0.5 at the resonance wavelength of 1550 nm. Six critical performance parameters were evaluated, including optical transmittance, contrast ratio, and insertion losses. The results showed exceptional performance, with the JK flip-flop achieving a transmittance over 3.067 in one operating condition with a nearly optimal (MD) of 92.8%. All components exhibited very low IL (-1.35 to -0.96 dB) despite their tiny size (250 × 410 nm²). The proposed design is crucial for photonic circuits and nanocircuits, especially for all-optical communication systems. These transmittances are attributed to the multiple inputs in the recommended designs. The suggested plasmonic flip-flop is simulated using the finite element approach in COMSOL Multiphysics.