High performance nanophotonic logic device for performing plasmonic D and T flip flops with 161 Tb/s bit rate

The major challenge of the fundamental building blocks of All-optical computer is the size of each element, including all optical logic gate, combinational, sequential circuits, and Arithmetic Logic Unit (ALU). This challenge can be overcome by plasmonic devices that solve problems related to size and the diffraction limit problems. This research proposes a new sequential logic circuits’ which is designed to perform the functionality of D and T flip–flops using plasmonic dielectric-metal-dielectric (DMD) multi-layer structure. The designed Nano-scale structure is simulated using Finite Element Method (FEM) and anisotropic transfer matrix method (aTMM). Here, D and T flip–flops are included on the same Nano-scale structure. The proposed structure operates on the basis of input-to-Ck signal interference, which can be both destructive and constructive. This research achieved the functionality of the proposed plasmonic flip–flops via twenty criteria, the main of them are: transmittance, contrast ratio (CR), modulation depth (MD), and insertion loss (IL) at 1550 nm. The results of the four criteria were; exceeding 100% in one state of D flip–flop and more than 70% in one state of T flip–flop in transmission, good and efficient CR by 9.16 dB and 9.75 dB for D and T flip–flops, respectively, efficient and optimum MD for both flip–flops duo to 90.3% and 98.7%, respectively, and lower insertion loss by − 1.2 dB and − 2.5 dB for D and T flip–flops, respectively. Bit rate is extremely very high-speed for both flip–flops duo to 161.6 Tb/s. in additionally, a response time is very fast about 6.2 fs which is obtained for the proposed plasmonic flipflops with ultra-compact footprint (350 nm *350 nm). Depending on these aspects, this device is very important to pave the way for using the nanophotonic computational circuits and as a fundamental building block for all-optical computers.