<p>Achieving reliable and efficient underfill encapsulation is critical for the performance and durability of modern flip-chip packaging, particularly in applications demanding miniaturization and high integration, such as AI-enabled mobile devices. This study systematically investigates the influence of substrate surface treatments, bump designs, and underfill material properties on flow dynamics, aiming to address key challenges such as void formation and incomplete filling. By employing advanced characterization techniques, the effects of plasma-treated photo solder resist (PSR) layers on surface roughness, wettability, and flow resistance were quantified. Bump array designs were analyzed to evaluate their impact on flow uniformity and void formation, revealing that less dense configurations enhance filling efficiency while denser arrays increase resistance and void risks. Comparative assessments of two underfill materials—underfill-A (UF-A) and underfill-B (UF-B)—highlighted the critical role of viscosity and filler size, with UF-A demonstrating superior flow due to its lower viscosity and smaller filler size. The findings demonstrate that optimizing PSR surface properties and underfill formulations is essential for achieving void-free encapsulation and efficient manufacturing. This work contributes to advancing flip-chip technology by providing a comprehensive understanding of the interplay between substrate, material, and design factors. The insights gained offer strategies to improve process reliability, reduce costs, and enhance the performance of semiconductor devices. These results have significant implications for the electronics industry, supporting the development of next-generation packaging solutions that meet the stringent demands of AI-driven and mobile technologies.</p>