Spiking Neural Networks (SNNs), best known for their complex spatial–temporal dynamics, event-driven features, and compatibility with neuromorphic hardware, are gaining popularity in brain-inspired intelligence. As a developing paradigm for artificial general intelligence (AGI), SNNs can potentially create more biologically plausible neural computation models. However, current artificial neural network circuit topologies struggle to accurately replicate the brain's sparse global and dense local connection patterns, also known as a small-world network. A new 3D Network-on-Chip (NoC) architecture and a hybrid wired-wireless NoC router are presented in this study to address this problem and facilitate effective on-chip connectivity in large-scale SNN simulations. The 3D NoC architecture is intended to deliver an accessible and high-performance architecture for mimicking brain-like connectivity inside a reconfigurable hardware environment. The system uses a Neural Tile (NT), which contains a 64:64 fully connected feed-forward SNN framework and incorporates a 3D mesh topology NoC connectivity framework. The hybrid NoC router, which combines wired and wireless routing paradigms, is developed to achieve high speed, reduced area, and increased reliability over standard wired or wireless-only systems. This design provides a viable method for effectively simulating large-scale SNNs and is demonstrated to be a more stable platform for high-performance neuromorphic computing. It addresses the challenge of delivering highly dynamic neural connectivity while maintaining efficient hardware usage. The paper offers a scalable platform for advancing the field of brain-inspired intelligence and neuro-engineering, which is essential for simulating and optimizing Spiking Neural Networks on neuromorphic hardware. The suggested framework has been assessed on a Xilinx Virtex-4 FPGA and synthesized using 90 nm low-power CMOS technology. The presented hybrid NoC router and 3D NoC-enabled architecture are thoroughly evaluated through simulation and synthesis. The proposed design with 64 neurons per chip achieves a silicon area of 3.072 mm2 on a Virtex-4 FPGA, compared to the 3.18 mm2 occupied by the 2D EMBRACE monolithic SNN architecture. This represents a 3.4% reduction in chip area, highlighting the space efficiency of the 3D NoC-based MCNT design, which is particularly impactful given the added scalability and vertical integration benefits of 3D architectures. The findings demonstrate that, compared to previous designs, the suggested architecture offers better performance, including lower latency, reduced chip area, and lower power consumption.

3D NoC-enabled spiking neural networks: a high-performance computing paradigm

期刊论文
发表日期：

2025年7月18日

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V. Karthikeyan,
K. Subbulakshmi

摘要

Spiking Neural Networks (SNNs), best known for their complex spatial–temporal dynamics, event-driven features, and compatibility with neuromorphic hardware, are gaining popularity in brain-inspired intelligence. As a developing paradigm for artificial general intelligence (AGI), SNNs can potentially create more biologically plausible neural computation models. However, current artificial neural network circuit topologies struggle to accurately replicate the brain's sparse global and dense local connection patterns, also known as a small-world network. A new 3D Network-on-Chip (NoC) architecture and a hybrid wired-wireless NoC router are presented in this study to address this problem and facilitate effective on-chip connectivity in large-scale SNN simulations. The 3D NoC architecture is intended to deliver an accessible and high-performance architecture for mimicking brain-like connectivity inside a reconfigurable hardware environment. The system uses a Neural Tile (NT), which contains a 64:64 fully connected feed-forward SNN framework and incorporates a 3D mesh topology NoC connectivity framework. The hybrid NoC router, which combines wired and wireless routing paradigms, is developed to achieve high speed, reduced area, and increased reliability over standard wired or wireless-only systems. This design provides a viable method for effectively simulating large-scale SNNs and is demonstrated to be a more stable platform for high-performance neuromorphic computing. It addresses the challenge of delivering highly dynamic neural connectivity while maintaining efficient hardware usage. The paper offers a scalable platform for advancing the field of brain-inspired intelligence and neuro-engineering, which is essential for simulating and optimizing Spiking Neural Networks on neuromorphic hardware. The suggested framework has been assessed on a Xilinx Virtex-4 FPGA and synthesized using 90 nm low-power CMOS technology. The presented hybrid NoC router and 3D NoC-enabled architecture are thoroughly evaluated through simulation and synthesis. The proposed design with 64 neurons per chip achieves a silicon area of 3.072 mm² on a Virtex-4 FPGA, compared to the 3.18 mm² occupied by the 2D EMBRACE monolithic SNN architecture. This represents a 3.4% reduction in chip area, highlighting the space efficiency of the 3D NoC-based MCNT design, which is particularly impactful given the added scalability and vertical integration benefits of 3D architectures. The findings demonstrate that, compared to previous designs, the suggested architecture offers better performance, including lower latency, reduced chip area, and lower power consumption.