<p>The architecture of the phase-locked loop (PLL), conceived in 1932 by H. Bellescize, initially to improve the process of frequency modulation, became a reference for all applications that require the detection and synchronization of electronic signals. Originally components of analog radio receivers, PLLs are ubiquitous in modern digital communication systems, now implemented as miniaturized integrated circuits that retain the same basic architecture. As part of faster communication and geographic localization devices, clock signal detection must have very high precision, and consequently, choosing PLL parameters is a fundamental task in designing devices following operational specifications. Consequently, analyzing perturbation effects on the PLL dynamics enables improvements in the performance of the clock distribution network. There are some classical works addressing noise effects considering stochastic differential equations applied to linear and nonlinear PLL architectures following a phase error reduction approach, i.e., considering the phase difference between input and output signals as the variable to be monitored and controlled. However, this difference is not directly measurable in real circuits, and, besides, adopting this way of modeling implies neglecting the double-frequency terms that result from the phase detection process. Here, we propose an approach that accounts for signal frequency behavior by directly using a state-space model. Consequently, accessible measurable signals are considered, and the action of the double-frequency components generated by the phase detection is taken into account. This modeling strategy, here called the phase non-reductionist approach, although analytically demanding, allows numerical and simulation strategies to define boundaries between synchronization and non-synchronization regions in the parameter space.</p>