This work presents an integrated area optimized hardware accelerator for generating public and private key pair for \(N^{th}\) degree Truncated polynomial Ring Units (NTRU) based Post Quantum Crypto (PQC) schemes, specifically for HRSS variant with tunable polynomials coefficients generation and sampling, and inversion hardware units. Typically, a key generation scheme is established in software considering the higher hardware resources required to generate polynomials, find inverses, and perform modulo multiplications. The software approach is optimal for one-time or infrequent key generation needs. Accelerating the key generation process by balancing the hardware resources (area) is essential for scenarios where keys are required to be generated dynamically during run-time at various sessions and instances in a resource-constrained environments like Internet of Things (IoT). This work addresses such needs and presents an area-optimized Key Generation hardware unit including tunable polynomial generation and inversion. True Random Number Generator (TRNG) and Linear Feedback Shift Registers (LFSRs) or TRNG and Block Cipher AES based Deterministic Random Binary Generator (CTR-DRBG) or TRNG and SHAKE256 engines along with the coefficients sampling unit generate the input polynomials, providing tunability in the choice of key generator. Constant Time Almost Inverse Algorithm (CT-AIA) based hardware unit does the inversions in \(\mathbb {S}_2\) , \(\mathbb {S}_3\) , \(\mathbb {R}_2\) , and \(\mathbb {R}_3\) , Almost Inverse Algorithm (AIA) hardware finds inverses in \(\mathbb {S}_q\) and \(\mathbb {R}_q\) , Montgomery Modular Multipliers (MMMs) perform polynomials multiplications in \(\mathbb {S}_3\) and \(\mathbb {R}_q\) for optimizing the area. The bit streams generated by TRNG-LFSRs, TRNG-CTR-DRBG, and TRNG-SHAKE256 which are based on stream-cipher, block-cipher, and hash-function crypto constructs, have been evaluated for entropy with NIST-SP-800-90B tests to ascertain the bit streams are indeed uniformly random and from Independent Identically Distributed (IID) sources. The hardware units for key generation and input polynomial generation have been integrated with a hardware accelerator for NTRU-HRSS701 for encryption / decryption which specifically need inverses in \(\mathbb {S}_3\) and \(\mathbb {R}_q\) which in-turn needs in \(\mathbb {S}_2\) , validated and tested using known answer test vectors (KAT) for NTRU-HRSS701. We have simulated and implemented the architecture on an FPGA platform, analyzed the results, and validated the outcomes. This work realizes a resource-optimized (area) hardware unit for dynamic key generation in NTRU-HRSS in IoT scenarios. The computational complexity of the key generation unit has been \(O(11N^2 + 4N)\) , dominated by polynomial inversions and multiplications in \(\mathbb {R}_q\) / \(\mathbb {S}_q\) .
