Scholarlink

<p>In this paper, a Trans-Impedance Amplifier (TIA) for ultra-low input current sensing in near-infrared spectroscopy (NIRS) wearable healthcare devices is presented. The proposed TIA consists of two stages to achieve a maximum transimpedance gain (TIG) of 239.86&#xa0;dBΩ. The −3&#xa0;dB bandwidth was 10&#xa0;MHz and the Unity Gain Bandwidth (UGB) was 100&#xa0;MHz. This TIA can sense and amplify ultra-low-input current in the range of 1&#xa0;pA to 10&#xa0;pA, and is used for wearable healthcare devices such as non-invasive glucometers and pulse oximeters. A novel variable trans-impedance gain control circuit and a saturation mitigation circuit were implemented. The input referred noise is 12.9&#xa0;fA/√Hz and the figure of Merit (FoM) is 2078. This TIA consumes 115.31&#xa0;µW of power at 27&#xa0;°C from a 1V supply voltage. The proposed circuit was implemented using a Generic Process Design Kit (GPDK) 45&#xa0;nm CMOS process. The layout occupied an area of 2264&#xa0;µm×2191&#xa0;µm.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

On the design and analysis of ultra low-input current sensing trans-impedance amplifier

  • 期刊论文

  • 发表日期：

    2025年8月23日

查看全文
  • B Muthukumaran,
  • B Ramachandran

摘要

In this paper, a Trans-Impedance Amplifier (TIA) for ultra-low input current sensing in near-infrared spectroscopy (NIRS) wearable healthcare devices is presented. The proposed TIA consists of two stages to achieve a maximum transimpedance gain (TIG) of 239.86 dBΩ. The −3 dB bandwidth was 10 MHz and the Unity Gain Bandwidth (UGB) was 100 MHz. This TIA can sense and amplify ultra-low-input current in the range of 1 pA to 10 pA, and is used for wearable healthcare devices such as non-invasive glucometers and pulse oximeters. A novel variable trans-impedance gain control circuit and a saturation mitigation circuit were implemented. The input referred noise is 12.9 fA/√Hz and the figure of Merit (FoM) is 2078. This TIA consumes 115.31 µW of power at 27 °C from a 1V supply voltage. The proposed circuit was implemented using a Generic Process Design Kit (GPDK) 45 nm CMOS process. The layout occupied an area of 2264 µm×2191 µm.