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<p>MoS<sub>2</sub>-based nonvolatile memory devices, including a capacitor and thin-film transistors (TFTs), were fabricated in a metal-MoS<sub>2</sub>-insulator-Si (MMIS) architecture with interfacial Au nanoparticles (Au NPs) serving as charge-storage nodes between monolayer MoS<sub>2</sub> and the gate dielectric. An n-type SiO<sub>2</sub> layer (10&#xa0;nm) was functionalized with an APTES self-assembled monolayer to enable dense Au NP assembly, yielding an M-capacitor with pronounced hysteresis in capacitance-voltage (C-V) characteristics. MoS<sub>2</sub> TFTs were further realized on 300&#xa0;nm n-type SiO<sub>2</sub>, either without Au NPs (M-TFT) or with the Au NP interlayer (MM-TFT). Solution-processed MoS<sub>2</sub> prepared by chemical exfoliation was characterized by TEM, AFM, Raman spectroscopy, and XPS. The M-capacitor exhibited a flat-band voltage shift (ΔV<sub>FB</sub>) of 1.73&#xa0;V under a ± 5&#xa0;V sweep, while the MM-TFT showed a threshold-voltage shift (ΔV<sub>TH</sub>) of 6.32&#xa0;V for a + 10 to -30&#xa0;V gate sweep, confirming efficient interfacial charge trapping.</p>

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Characteristics of the MoS2 Memory Thin Film Transistor With Au Nanoparticles Embedded as Charging Elements

  • 期刊论文

  • 发表日期：

    2026年5月19日

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  • Tae Seok Seo

摘要

MoS2-based nonvolatile memory devices, including a capacitor and thin-film transistors (TFTs), were fabricated in a metal-MoS2-insulator-Si (MMIS) architecture with interfacial Au nanoparticles (Au NPs) serving as charge-storage nodes between monolayer MoS2 and the gate dielectric. An n-type SiO2 layer (10 nm) was functionalized with an APTES self-assembled monolayer to enable dense Au NP assembly, yielding an M-capacitor with pronounced hysteresis in capacitance-voltage (C-V) characteristics. MoS2 TFTs were further realized on 300 nm n-type SiO2, either without Au NPs (M-TFT) or with the Au NP interlayer (MM-TFT). Solution-processed MoS2 prepared by chemical exfoliation was characterized by TEM, AFM, Raman spectroscopy, and XPS. The M-capacitor exhibited a flat-band voltage shift (ΔVFB) of 1.73 V under a ± 5 V sweep, while the MM-TFT showed a threshold-voltage shift (ΔVTH) of 6.32 V for a + 10 to -30 V gate sweep, confirming efficient interfacial charge trapping.