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<p>Approximate computing is an efficient design approach that reduces energy consumption while allowing a tolerable loss in accuracy. The proposed low-power approximate Booth multiplier (PABM) integrates two novel radix-4 Booth encoders—R4BEYOGA1 and R4BEYOGA2—and the proposed Cyoga 4:2 compressor. This design optimizes power and circuit complexity through truncation, exact, and approximate sections. The Cyoga compressor achieves a 49% power reduction, 61.1% area reduction, and 94% fewer transistors in pre-layout, with a 50% power reduction, 61.1% area reduction, and 27.4% lower delay post-layout. The R4BEYOGA1 encoder reduces power by 38.2% and area by 35.2% compared to exact encoders. Post-layout, PABM shows 29% lower power, 44% reduced power-delay product (PDP), and 27% smaller area than exact multipliers. The R4BMYOGA1 multiplier using Long Short-Term Memory (LSTM) is the most efficient, achieving 77.9% lower power consumption and 77.2% smaller area than Exactwc. Performance evaluations using error metrics such as the error rate (ER), mean error distance (MED), normalized mean error distance (NMED), mean square error (MSE), and error distance (ED) and neural network-based analysis confirm the proposed designs' superior accuracy, making them ideal for error-tolerant applications such as image processing. The designs are synthesized using a 90&#xa0;nm CMOS technology library and validated through simulations in Modelsim and MATLAB, revealing significant enhancements in image processing tasks, notably in sharpening and smoothing, with R4BMYOGA1 delivering the best Peak Signal-to-Noise Ratio (PSNR) of 33.37 dB.</p>

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Power-efficient approximate booth multiplier using novel radix-4 encoders and a 4:2 compressor for high-performance cognitive vision applications

  • 期刊论文

  • 发表日期：

    2026年3月9日

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  • Yogeswari Palanisamy,
  • Kathirvelu Murugan

摘要

Approximate computing is an efficient design approach that reduces energy consumption while allowing a tolerable loss in accuracy. The proposed low-power approximate Booth multiplier (PABM) integrates two novel radix-4 Booth encoders—R4BEYOGA1 and R4BEYOGA2—and the proposed Cyoga 4:2 compressor. This design optimizes power and circuit complexity through truncation, exact, and approximate sections. The Cyoga compressor achieves a 49% power reduction, 61.1% area reduction, and 94% fewer transistors in pre-layout, with a 50% power reduction, 61.1% area reduction, and 27.4% lower delay post-layout. The R4BEYOGA1 encoder reduces power by 38.2% and area by 35.2% compared to exact encoders. Post-layout, PABM shows 29% lower power, 44% reduced power-delay product (PDP), and 27% smaller area than exact multipliers. The R4BMYOGA1 multiplier using Long Short-Term Memory (LSTM) is the most efficient, achieving 77.9% lower power consumption and 77.2% smaller area than Exactwc. Performance evaluations using error metrics such as the error rate (ER), mean error distance (MED), normalized mean error distance (NMED), mean square error (MSE), and error distance (ED) and neural network-based analysis confirm the proposed designs' superior accuracy, making them ideal for error-tolerant applications such as image processing. The designs are synthesized using a 90 nm CMOS technology library and validated through simulations in Modelsim and MATLAB, revealing significant enhancements in image processing tasks, notably in sharpening and smoothing, with R4BMYOGA1 delivering the best Peak Signal-to-Noise Ratio (PSNR) of 33.37 dB.