<p>Approximate computing offers a promising paradigm for energy-efficient hardware design by trading minimal precision for substantial gains in power and performance. This paper introduces the Modified Dadda Approximate Multiplier (MDAM), an innovative architecture that optimizes hardware economy, reduces power consumption, and delivers enhanced accuracy for applications including convolutional neural networks (CNNs) and image processing. Standard multipliers employed in CNNs are computationally intensive and energy-demanding, limiting their deployment in edge devices and real-time scenarios. The proposed MDAM leverages approximate computing techniques to balance accuracy with reduced power consumption, area, and processing time while maintaining acceptable performance for CNN tasks. Through its modified structure, MDAM achieves significant complexity reduction by minimizing partial products and streamlining carry propagation phases. The design incorporates error compensation mechanisms, truncation strategies, and a novel 4:2 Approximate Compressor (AC) to optimize the performance-error trade-off. Extensive experiments across multiple CNN models for image classification and object detection tasks validate the effectiveness of this approach. Both 8-bit and 16-bit versions of existing approximate multipliers (AMs) were implemented in Verilog and synthesized using MATLAB, Xilinx Vivado, and Cadence RTL Compiler for comprehensive performance evaluation. Comparative simulations demonstrate MDAM's superiority across key design metrics: up to 37.5% reduction in power consumption, 46.6% decrease in delay, and 25.9% reduction in area compared to prior designs. These improvements position MDAM as particularly advantageous for embedded systems and energy-efficient CNN applications. The multiplier's effectiveness was further validated through successful implementation in image processing and CNN inference tasks, confirming its practical viability for error-tolerant computing applications.</p>