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<p>An electroencephalogram is a technique to record the brain’s electrical activity. It is a critical tool in diagnosing several disorders, such as sleep apnea. Hence, proper artifact removal from the EEG signal is indispensable. Since it is the recording of brain activity, there is a high susceptibility to error due to other biomedical signals. As a consequence, the removal of other signals or noise is critical to the accurate diagnosis of disorders. Many uses related to the EEG signal are real-time applications; hence, hardware-based denoising is the most viable solution. Area efficiency is one of the most important parameters to be considered in a FPGA-based system. Therefore, in this study, an area-efficient integration of an optimized cascaded least mean squared filter and a Teager–Kaiser energy operator is done. The cascaded LMS filter is then enhanced using distributed arithmetic and pipelining. Further, the Teager–Kaiser energy operator is refined by applying an approximate squarer. Then, this integration is compared with existing denoising techniques. This comparison has shown a reduction in area of almost 47% in registers and 61.2% decrease in terms of look-up tables. This architecture was synthesized using Xilinx Vivado 19.1, and the hardware description language used is Verilog HDL.</p>

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An area efficient FPGA design for EEG signal denoising using LMS adaptive filtering and Teager–Kaiser energy operator

  • 期刊论文

  • 发表日期：

    2025年4月15日

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  • Suma Nair,
  • Britto Pari James

摘要

An electroencephalogram is a technique to record the brain’s electrical activity. It is a critical tool in diagnosing several disorders, such as sleep apnea. Hence, proper artifact removal from the EEG signal is indispensable. Since it is the recording of brain activity, there is a high susceptibility to error due to other biomedical signals. As a consequence, the removal of other signals or noise is critical to the accurate diagnosis of disorders. Many uses related to the EEG signal are real-time applications; hence, hardware-based denoising is the most viable solution. Area efficiency is one of the most important parameters to be considered in a FPGA-based system. Therefore, in this study, an area-efficient integration of an optimized cascaded least mean squared filter and a Teager–Kaiser energy operator is done. The cascaded LMS filter is then enhanced using distributed arithmetic and pipelining. Further, the Teager–Kaiser energy operator is refined by applying an approximate squarer. Then, this integration is compared with existing denoising techniques. This comparison has shown a reduction in area of almost 47% in registers and 61.2% decrease in terms of look-up tables. This architecture was synthesized using Xilinx Vivado 19.1, and the hardware description language used is Verilog HDL.