Hardware implementation of digital pseudo-random number generators for real-time applications

This paper introduces the hardware implementation of Digital Pseudo-Random Number Generators (DPRNG) based on chaotic systems. First, high-performance pipeline hardware architectures, respectively, for the 3D Lorenz, 3D Chua, 3D Rossler, and 3D Chen chaotic systems are designed to increase the operating frequency. The study also includes an examination of the hardware architectures with 32-bit fixed-point and 32-bit single floating-point data precision. Second, hardware architectures of DPRNG based on a single chaotic system and the congruential generator are put forward. Third, a robust DPRNG, that mixes the 3D Lorenz, 3D Chua, 3D Rossler, and 3D Chen chaotic systems is proposed where all designed chaotic systems operate in parallel. This architecture increases pseudo-random numbers space up to 2⁴⁸⁰. The FPGA implementation of the proposed pipeline hardware architecture of the complex DPRNG can achieve a maximal operating frequency of 192.446 MHz with a high throughput of 73,899.264 Mbps. The NIST 800-22 test suite result indicates that the DPRNG produces high-quality pseudo-random bits. Consequently, the proposed DPRNG is deemed suitable for use in high-speed applications.