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<p>In advanced semiconductor devices at 7&#xa0;nm and below, lower back-end-of-line interconnect layers and&#xa0;via gate/contact structures approach sub-100&#xa0;nm thickness. At these dimensions, millimeter-scale planar exposure is required to enable full-die mapping, distributed defect analysis via chain continuity evaluation, and architectural verification. However, conventional delayering techniques remain limited by either the lateral field of view, nonuniform material removal, or operator dependence. A new automated broad ion beam delayering methodology enables planarization across millimeter-scale areas while maintaining nanometer-scale uniformity. The system integrates ion milling and real-time scanning electron microscopy surface metrology in a single chamber. It operates as a closed-loop process comprising ion milling, data acquisition, surface-state evaluation, and adaptive adjustment of milling parameters. A final low-energy (1&#xa0;keV) ion beam&#xa0;polishing step is incorporated to minimize the ion-induced damage layer, improving preservation of transistor features and enabling subsequent high-resolution structural and electrical characterization. Application of the methodology to advanced system-on-chip devices demonstrates a reduction in the initial ± 60&#xa0;nm surface nonuniformity (after mechanical preparation) to within 20&#xa0;nm across a 5&#xa0;mm-diameter region. Sequential exposure from upper metal layers down to via gate/contact levels was achieved while preserving fragile interconnect and dielectric structures. The resulting planar surface enabled simultaneous visualization of multiple functional domains—including processing cores, cache regions, logic blocks, and extended via chains—within a single delayered plane. This capability establishes a scalable pathway for full-die structural analysis and represents a transformative step beyond site-specific delayering for the semiconductor industry.</p>

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Deterministic Millimeter-Scale Delayering for Advanced Semiconductor Failure Analysis and Reverse Engineering

  • 期刊论文

  • 发表日期：

    2026年7月31日

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  • Pawel Nowakowski,
  • Michael Boccabella,
  • Richard Wei-Chih Li,
  • Mary Ray,
  • Paul Fischione

摘要

In advanced semiconductor devices at 7 nm and below, lower back-end-of-line interconnect layers and via gate/contact structures approach sub-100 nm thickness. At these dimensions, millimeter-scale planar exposure is required to enable full-die mapping, distributed defect analysis via chain continuity evaluation, and architectural verification. However, conventional delayering techniques remain limited by either the lateral field of view, nonuniform material removal, or operator dependence. A new automated broad ion beam delayering methodology enables planarization across millimeter-scale areas while maintaining nanometer-scale uniformity. The system integrates ion milling and real-time scanning electron microscopy surface metrology in a single chamber. It operates as a closed-loop process comprising ion milling, data acquisition, surface-state evaluation, and adaptive adjustment of milling parameters. A final low-energy (1 keV) ion beam polishing step is incorporated to minimize the ion-induced damage layer, improving preservation of transistor features and enabling subsequent high-resolution structural and electrical characterization. Application of the methodology to advanced system-on-chip devices demonstrates a reduction in the initial ± 60 nm surface nonuniformity (after mechanical preparation) to within 20 nm across a 5 mm-diameter region. Sequential exposure from upper metal layers down to via gate/contact levels was achieved while preserving fragile interconnect and dielectric structures. The resulting planar surface enabled simultaneous visualization of multiple functional domains—including processing cores, cache regions, logic blocks, and extended via chains—within a single delayered plane. This capability establishes a scalable pathway for full-die structural analysis and represents a transformative step beyond site-specific delayering for the semiconductor industry.