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<p>The relentless pursuit of high-performance computing driven by 5G/6G, artificial intelligence, autonomous driving, Internet of things (IoT), quantum computing, and data centers has pushed traditional integrated circuit scaling to its limits&#xa0;[<CitationRef CitationID="CR1">1</CitationRef>]. As lithography challenges and escalating manufacturing costs slow Moore’s law, the industry has pivoted toward design technology co-optimization (DTCO) and system technology co-optimization (STCO). These methodologies extend device performance through process and package scaling, introducing complex transistor architectures like gate-all-around (GAA), forksheets, and complementary FETs (CFET), alongside system-level innovations like backside power deliver networks (BPDN), 3D IC, and heterogeneous integration. While these advancements optimize power, performance, area, and cost (PPAC), they inadvertently create a significant bottleneck in failure analysis (FA). Advanced package technologies such as co-packaged optics, heterogeneous integration, and chiplets have fundamentally disrupted electrical fault isolation (EFI) flows. Complex package routing and dense 3D stacking of multiple components now pose severe challenges to fault isolation. Historically, the industry relied on design for test (DFT) to screen defects and design for diagnosis (DFD) to predict failure locations. However, in advanced nodes, diagnostic quality is often insufficient to characterize underlying failure mechanisms, and design complexity restricts accessibility and controllability of internal signals needed for EFI. This paper reviews the impact of DTCO and STCO on failure analysis, identifying key challenges and drivers. FA has traditionally been treated as a post-silicon afterthought; chip and hardware designs rarely consider its workflows. Yet, as new technologies evolve, FA becomes a critical bottleneck to yield learning, slowing down yield ramp-up and time-to-market. This paper calls for a strategic “left-shift” of FA requirements early into the design cycle through design for analysis (DFA). By integrating dedicated DFA features, manufacturers can bridge the gap between silicon design and post-silicon debug, transforming FA into a proactive driver of yield.</p>

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Challenges and Strategic Drivers in 3D IC Failure Analysis: Closing the Critical Gaps using Designs for Analysis

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年8月1日

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  • Lesly Zaren Endrinal,
  • Willem D. van Driel,
  • Guo Qi Zhang

摘要

The relentless pursuit of high-performance computing driven by 5G/6G, artificial intelligence, autonomous driving, Internet of things (IoT), quantum computing, and data centers has pushed traditional integrated circuit scaling to its limits [1]. As lithography challenges and escalating manufacturing costs slow Moore’s law, the industry has pivoted toward design technology co-optimization (DTCO) and system technology co-optimization (STCO). These methodologies extend device performance through process and package scaling, introducing complex transistor architectures like gate-all-around (GAA), forksheets, and complementary FETs (CFET), alongside system-level innovations like backside power deliver networks (BPDN), 3D IC, and heterogeneous integration. While these advancements optimize power, performance, area, and cost (PPAC), they inadvertently create a significant bottleneck in failure analysis (FA). Advanced package technologies such as co-packaged optics, heterogeneous integration, and chiplets have fundamentally disrupted electrical fault isolation (EFI) flows. Complex package routing and dense 3D stacking of multiple components now pose severe challenges to fault isolation. Historically, the industry relied on design for test (DFT) to screen defects and design for diagnosis (DFD) to predict failure locations. However, in advanced nodes, diagnostic quality is often insufficient to characterize underlying failure mechanisms, and design complexity restricts accessibility and controllability of internal signals needed for EFI. This paper reviews the impact of DTCO and STCO on failure analysis, identifying key challenges and drivers. FA has traditionally been treated as a post-silicon afterthought; chip and hardware designs rarely consider its workflows. Yet, as new technologies evolve, FA becomes a critical bottleneck to yield learning, slowing down yield ramp-up and time-to-market. This paper calls for a strategic “left-shift” of FA requirements early into the design cycle through design for analysis (DFA). By integrating dedicated DFA features, manufacturers can bridge the gap between silicon design and post-silicon debug, transforming FA into a proactive driver of yield.