<p>As System-on-a-Chip (SoC) continues to increase in complexity, multiple functionalities are being integrated into one integrated circuit (IC). This requires optimization of the Design-for-Testability (DFT) architecture to minimize test time while keeping full test coverage of the entire chip. This initiative has led to the widespread adoption of Tessent Streaming Scan Network (SSN) architecture on advanced technology nodes. Unlike traditional scan architectures that send data directly to the scan chains, SSN breaks down the data into packets and optimizes the delivery of these packets to allow efficient, concurrent testing of any number of cores. However, the implementation of the SSN architecture presents a challenge for failure analysis, as it becomes extremely difficult to directly modify the SSN patterns on the fly to create a stimulus that will be used for many of the electrical fault isolation (EFI) techniques such as Laser Voltage Imaging (LVI) and Probing (LVP), Dynamic Laser Stimulation (DLS) and Photon Emissions Analysis (PEM). Key challenges include the inability to loop test patterns, run periodic sequences and no visibility of the scan control and clock signals, since these signals are internally generated by the SSH during retargeting. This paper introduces a new Tessent DFT enhancement developed by Siemens called the “LVX mode.” It is the first feature designed to enable Failure Analysis within a DFT tool, utilizing a specific DFT hardware implementation. This paper also presents another new DFT feature that provides special pattern annotations which indicate the start and end of a capture window per pattern per core and the subsequent time stamp locations of each capture pulse within that window for a particular pattern of interest. This new capability allows for static photon emissions by stopping the pattern before any capture event, as will be illustrated in our methodology. Because SSN patterns cannot be modified on the fly, this paper presents two methods for more effective and efficient DLS looping. First method involves pattern truncation, which is straightforward and more suitable for foundry debug, while the second method involving pattern generation allows for quicker DLS runs due to the shorter length of the patterns. We will briefly discuss some of the methodologies employed to optimize the pattern generation process for FA. Finally, the paper will demonstrate the effectiveness of these DFT enhancements for EFI through several use cases.</p>