Detection and Localization of Undesired Quasi-Static Transitions in a Scan Flip-Flop

Quasi-static transition failures in the main logic of modern semiconductors devices are very challenging to be detected in a standard test production environment, because they need a lot of test time to be activated, and usually this is not compatible with a reasonable test time. Many semiconductor manufacturers usually agree not to test these process marginalities to avoid increasing the total cost of the device so much, but accept a few ppm of returns from the customer. In general we are talking about a few decimals of ppm. The typical cases that we can encounter are retention failures in flip-flops, unexpected set, or reset happening after tens of milliseconds. The aim of this work is to discuss the technique/method to deal with quasi-static transition failures. The paper also proposes one possible strategy to detect and locate them in a failure analysis test environment making a benchmark between the most appropriate fault localization technique.