This paper presents a simulated study on a two-dimensional (2D) gate-all-around (GAA) dielectric pocket (DP) with tri-metal nanowire metal–oxide–semiconductor field-effect transistor (MOSFET), designed to mitigate short-channel effects (SCEs) in 7-nm devices using semiconductor-on-insulator (SOI) technology. The proposed architecture incorporates HfO2 dielectric pockets at the source and drain ends, a p-type doped channel, n-type source/drain regions, and a tri-metal gate structure with work functions ranging from 4.6 eV to 5.0 eV, enclosed by high-k (HfO2) and low-k (SiO2, vacuum) dielectric pairs. Simulations were conducted using the Silvaco ATLAS TCAD (technology computer-aided design) tool to demonstrate superior electrostatic control, with surface potential ranging from 0.3 V to 0.9 V, drain current between 8.4 × 10−9 A and 1.12 × 10−5 A, and a subthreshold slope of approximately 63 mV/dec. The device achieves high transconductance (1.1 × 10−5 S), cutoff frequencies peaking at 8 × 105 GHz, and a frequency–transconductance product of 5 × 105 Hz/V. The vacuum-Si3N4 produces a maximum gain of 6 dB, highlighting its suitability for high-performance analog and digital applications. With a 5-nm channel length, this design aligns with the International Roadmap for Devices and Systems (IRDS) projections for 7-nm, 5-nm, and 3-nm nodes, offering a scalable and high-efficiency solution for next-generation nanoelectronics. Key performance metrics calculated include gate capacitance (Cgg versus Vgs) gate–source/drain capacitances (Cgd, Cgs), drain current (Ids versus Vds), Sqrt(Ids), transconductance (Gm), subthreshold slope (SS), cutoff frequency (fT), frequency–transconductance product (FTP), transconductance generation factor (TGF), gain (Av), switching time (τ), Ion, Ioff, Ion / Ioff, log10 (Ids), valence and conduction band energies, electron mobility, surface potential, electric field, and quasi-Fermi level (QFL) across various dielectric pairs and gate work functions.

Design and Performance Analysis of a 5-nm GAA Nanowire MOSFET Using Dielectric Pocket Engineering and Tri-Metal High-k Gate Architecture

期刊论文
发表日期：

2026年7月4日

查看全文

A. Swetha,
B. Balaji,
Rajyalakshmi Uppada,
Narayana Rao Palepu,
Sreevardhan Cheerla,
Vipul Agarwal,
Lakshmana Kumar Muthbatula,
Sreenivas Rao Devireddy,
Y. Gowthami,
Lokendra Singh,
Biswajit Jena

摘要

This paper presents a simulated study on a two-dimensional (2D) gate-all-around (GAA) dielectric pocket (DP) with tri-metal nanowire metal–oxide–semiconductor field-effect transistor (MOSFET), designed to mitigate short-channel effects (SCEs) in 7-nm devices using semiconductor-on-insulator (SOI) technology. The proposed architecture incorporates HfO₂ dielectric pockets at the source and drain ends, a p-type doped channel, n-type source/drain regions, and a tri-metal gate structure with work functions ranging from 4.6 eV to 5.0 eV, enclosed by high-k (HfO₂) and low-k (SiO₂, vacuum) dielectric pairs. Simulations were conducted using the Silvaco ATLAS TCAD (technology computer-aided design) tool to demonstrate superior electrostatic control, with surface potential ranging from 0.3 V to 0.9 V, drain current between 8.4 × 10⁻⁹ A and 1.12 × 10⁻⁵ A, and a subthreshold slope of approximately 63 mV/dec. The device achieves high transconductance (1.1 × 10⁻⁵ S), cutoff frequencies peaking at 8 × 10⁵ GHz, and a frequency–transconductance product of 5 × 10⁵ Hz/V. The vacuum-Si₃N₄ produces a maximum gain of 6 dB, highlighting its suitability for high-performance analog and digital applications. With a 5-nm channel length, this design aligns with the International Roadmap for Devices and Systems (IRDS) projections for 7-nm, 5-nm, and 3-nm nodes, offering a scalable and high-efficiency solution for next-generation nanoelectronics. Key performance metrics calculated include gate capacitance (C_gg versus V_gs) gate–source/drain capacitances (C_gd, C_gs), drain current (I_ds versus V_ds), Sqrt(I_ds), transconductance (G_m), subthreshold slope (SS), cutoff frequency (f_T), frequency–transconductance product (FTP), transconductance generation factor (TGF), gain (A_v), switching time (τ), I_on, I_off, I_on / I_off, log₁₀ (I_ds), valence and conduction band energies, electron mobility, surface potential, electric field, and quasi-Fermi level (QFL) across various dielectric pairs and gate work functions.