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<p>According to Moore’s law, the number of transistors on a chip is anticipated to double approximately every 2&#xa0;years. Over the past decades, metal–organic–semiconductor field-effect transistor (MOSFET) technology has undergone aggressive scaling to keep pace with this trend. However, as transistor dimensions approach their physical limits (e.g., 22&#xa0;nm), several drawbacks have emerged, including high leakage current, short-channel effects (SCEs), and velocity saturation. As a result, alternative technologies to conventional MOSFETs are needed for the energy-efficient design of circuits. In this paper, we introduce and comprehensively describe several alternatives to 22-nm MOSFET technology, including fin field-effect transistors (FinFETs, at 20&#xa0;nm, 16&#xa0;nm, 14&#xa0;nm, 10&#xa0;nm, and 7&#xa0;nm), graphene nanoribbon FETs (GNRFETs at 16&#xa0;nm), top-gate carbon nanotube FETs (TG-CNTFETs at 32&#xa0;nm), and gate-all-around CNTFETs (GAA-CNTFETs at 10&#xa0;nm). Each of these technologies presents distinct advantages and disadvantages. To evaluate their performance, we analyze them as n-channel transistors and assess their implementation in digital circuits, such as NOT gates and computational units (full adders, full subtractors, and 4:2 compressors). Simulation results using HSPICE demonstrate that circuits utilizing GNRFET-16&#xa0;nm, TG-CNTFET-32&#xa0;nm, and GAA-CNTFET-10&#xa0;nm technologies exhibit superior power–delay product (PDP) and power–delay–area product (PDAP) values compared to other technologies. Consequently, these alternatives show strong potential for replacing traditional MOSFETs in the energy-efficient design of computational circuits.</p>

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A Comparative Study on Nano-Transistors and Their Performance in Design of Energy-Efficient Computational Circuits

  • 期刊论文

  • 发表日期：

    2025年10月7日

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  • Majid Amini-Valashani,
  • Sattar Mirzakuchaki

摘要

According to Moore’s law, the number of transistors on a chip is anticipated to double approximately every 2 years. Over the past decades, metal–organic–semiconductor field-effect transistor (MOSFET) technology has undergone aggressive scaling to keep pace with this trend. However, as transistor dimensions approach their physical limits (e.g., 22 nm), several drawbacks have emerged, including high leakage current, short-channel effects (SCEs), and velocity saturation. As a result, alternative technologies to conventional MOSFETs are needed for the energy-efficient design of circuits. In this paper, we introduce and comprehensively describe several alternatives to 22-nm MOSFET technology, including fin field-effect transistors (FinFETs, at 20 nm, 16 nm, 14 nm, 10 nm, and 7 nm), graphene nanoribbon FETs (GNRFETs at 16 nm), top-gate carbon nanotube FETs (TG-CNTFETs at 32 nm), and gate-all-around CNTFETs (GAA-CNTFETs at 10 nm). Each of these technologies presents distinct advantages and disadvantages. To evaluate their performance, we analyze them as n-channel transistors and assess their implementation in digital circuits, such as NOT gates and computational units (full adders, full subtractors, and 4:2 compressors). Simulation results using HSPICE demonstrate that circuits utilizing GNRFET-16 nm, TG-CNTFET-32 nm, and GAA-CNTFET-10 nm technologies exhibit superior power–delay product (PDP) and power–delay–area product (PDAP) values compared to other technologies. Consequently, these alternatives show strong potential for replacing traditional MOSFETs in the energy-efficient design of computational circuits.