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<p>This work proposes an investigation of silicon-on-insulator (SOI) tunnel field-effect transistors (TFETs) with an extended source (ES) into the channel region along with gate overlap on the source for direct current (DC) and analog applications. The proposed SOI-ES-gate-on-source (GoS) TFET structure exploits both line and point tunneling mechanisms to mitigate ambipolar current, simultaneously improving the on-state current. These benefits include low off-state current, better subthreshold swing, and endurance to short-channel effects. With its optimal architecture, the proposed SOI-ES-GoS TFET provides a high on/off current ratio of 6.88 × 10<sup>10</sup>, a small subthreshold swing (SS) of 9.9&#xa0;mV/decade, and a low threshold voltage (<i>V</i><sub>th</sub>) of 0.2&#xa0;V. The viability of SOI-ES-GoS TFET for both DC and analog/radio frequency (RF) applications was also determined by analyzing the analog/RF performance parameters C<sub>gg</sub>, C<sub>gs</sub>, C<sub>gd</sub>, cutoff frequency, transconductance, g<sub>d</sub>, GBP, transconductance generation factor (TGF), and transconductance frequency product (TFP). Moreover, the performance of the proposed device was analyzed under uniform and Gaussian interface traps at both the buried oxide/silicon and the oxide/channel interfaces to ascertain its reliability concerns.</p>

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Exploration of the Performance of SOI-Tunnel FETs with Extended Source for DC and Analog Applications

  • 期刊论文

  • 发表日期：

    2025年8月23日

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  • B. V. Rao,
  • Arun Kumar,
  • Sirisha Meriga,
  • Brinda Bhowmick

摘要

This work proposes an investigation of silicon-on-insulator (SOI) tunnel field-effect transistors (TFETs) with an extended source (ES) into the channel region along with gate overlap on the source for direct current (DC) and analog applications. The proposed SOI-ES-gate-on-source (GoS) TFET structure exploits both line and point tunneling mechanisms to mitigate ambipolar current, simultaneously improving the on-state current. These benefits include low off-state current, better subthreshold swing, and endurance to short-channel effects. With its optimal architecture, the proposed SOI-ES-GoS TFET provides a high on/off current ratio of 6.88 × 1010, a small subthreshold swing (SS) of 9.9 mV/decade, and a low threshold voltage (Vth) of 0.2 V. The viability of SOI-ES-GoS TFET for both DC and analog/radio frequency (RF) applications was also determined by analyzing the analog/RF performance parameters Cgg, Cgs, Cgd, cutoff frequency, transconductance, gd, GBP, transconductance generation factor (TGF), and transconductance frequency product (TFP). Moreover, the performance of the proposed device was analyzed under uniform and Gaussian interface traps at both the buried oxide/silicon and the oxide/channel interfaces to ascertain its reliability concerns.