<p>We investigate the impact of epitaxial layer pits on the electrical characteristics of 4H silicon carbide (4H-SiC) junction barrier Schottky (JBS) diodes. The size and spatial distribution of these pits are characterized using atomic force microscopy (AFM) and defect detectors to align with the positions of the fabricated JBS devices on the 4H-SiC epitaxial wafer. It was confirmed that the presence of pits causes a local electric field enhancement, which leads to a decrease in the device breakdown voltage. Furthermore, an increase in the aspect ratio of the pits can significantly reduce the breakdown voltage. Additionally, an increase in pit density correlates with a more significant reduction in breakdown voltage; however, beyond a specific threshold, the magnitude of breakdown voltage reduction stabilizes and remains unaffected by further increases in pit density. To mitigate pit formation and enhance device performance, we separately investigated the effects of growth temperature, carbon-to-silicon (C/Si) ratio, and growth rate on pit density. Experimental results show that lower C/Si ratios and lower epitaxial growth rates effectively decrease pit density. At a C/Si ratio of 0.8, the pit density is controlled to 1.5&#xa0;cm⁻², while at a growth rate of 45&#xa0;μm/h, the pit density is predominantly below 15&#xa0;cm⁻². Meanwhile, it was observed that 4H-SiC epitaxial layers grown at a growth temperature of 1605°C generally exhibit lower pit density.</p>