Design and Realization of Novel Dual-Input Logic Gates using Virtual Doped Junctionless Double-Gate TFETs
摘要
This paper presents the realization of two-input logic functions in a single device using a virtual doped junctionless double-gate tunnel field-effect transistor (VD-JL-DGTFET). The main objective of this work is to significantly reduce the number of transistors required for logic gate design by making structural changes and optimizing critical parameters such as silicon body thickness and gate work function. The proposed VD-JL-DGTFET structure has been validated through Silvaco TCAD simulations. The simulation results demonstrate that the required logic operations are achievable with significantly lower power consumption. It is possible to achieve OR and AND functions with the n-type configuration and NAND and NOR functionalities with the p-type configuration, through independent biasing of the top and bottom gates for different input logic combinations. Results from the simulations show that ON-state current for OR and NAND gates is approximately 4.10 × 10−7 A/μm and the ION/IOFF ratio is around 1010, at VDD = 0.5 V. More efficient integrated circuits are anticipated through this structural design change, which significantly reduces power usage and transistor count. These findings demonstrate the potential of the device for use in future low-power applications.