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<p>The easy fabrication process of a junctionless nanowire field-effect transistor (JL-NWFET) positions it as a promising alternative to the conventional FET. However, the heavy doping required in the JL-NWFET restricts carrier mobility and volume depletion. This paper introduces a dual-material gate (DMG) and a core–shell (CS) structure in the JL-NWFET to address these challenges. Moreover, developing an analytical model is crucial for understanding the intricate details of device physics. A physics-based 2D analytical model for the DMG-CS JL-NWFET is proposed in this paper. Using an analytical model, the subthreshold characteristics of the DMG-CS-JL-NWFET are investigated in terms of surface potential, electric field, threshold voltage, subthreshold drain current, leakage current (<i>I</i><sub>OFF</sub>), <i>I</i><sub>ON</sub>/<i>I</i><sub>OFF</sub> ratio, subthreshold slope, and drain-induced barrier lowering (DIBL). The simulation results obtained with the ATLAS 3D device simulator align with the analytical results. The proposed model can serve as a foundational design guideline for core–shell-incorporated gate-engineered JL-NWFETs.</p>

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Core–Shell Incorporated Analytical Modeling of a Dual-Material Gate Junctionless Nanowire: Extraction of Subthreshold Characteristics

  • 期刊论文

  • 发表日期：

    2025年1月30日

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  • Bharti,
  • Poornima Mittal

摘要

The easy fabrication process of a junctionless nanowire field-effect transistor (JL-NWFET) positions it as a promising alternative to the conventional FET. However, the heavy doping required in the JL-NWFET restricts carrier mobility and volume depletion. This paper introduces a dual-material gate (DMG) and a core–shell (CS) structure in the JL-NWFET to address these challenges. Moreover, developing an analytical model is crucial for understanding the intricate details of device physics. A physics-based 2D analytical model for the DMG-CS JL-NWFET is proposed in this paper. Using an analytical model, the subthreshold characteristics of the DMG-CS-JL-NWFET are investigated in terms of surface potential, electric field, threshold voltage, subthreshold drain current, leakage current (IOFF), ION/IOFF ratio, subthreshold slope, and drain-induced barrier lowering (DIBL). The simulation results obtained with the ATLAS 3D device simulator align with the analytical results. The proposed model can serve as a foundational design guideline for core–shell-incorporated gate-engineered JL-NWFETs.