On-Current Improvement in Bulk-Accumulated Double-Gate ZnO TFT

Channel thickness is a key parameter in determining the electrical characteristics of double-gate ZnO thin film transistors (DGTFTs). In thicker channels, the accumulation region is confined to the ZnO/SiO₂ (semiconductor/gate dielectric) interface. However, in such devices with ultrathin channels, the accumulation region extends the entire depth of the channel. This work investigates the impact of channel thickness on the electrical characteristics of a double-gate ZnO TFT in the grounded top gate (GTG) and common mode gate (CMG) biasing modes. Gaussian distributed traps are assumed to be present at the ZnO/SiO₂ interface with a peak concentration of 10¹² cm⁻² eV⁻¹ to accurately represent the interface. From technology computer-aided design simulations, it is concluded that in CMG mode, a bulk-accumulated 5-nm-thick DGTFT shows a 15- fold improvement in ON current as compared to its GTG counterpart. However, a 500-nm-thick DGTFT CMG mode shows merely twofold improvement in ON current compared to GTG mode.