Spacer Engineered Halo-Doped Nanowire MOSFET for Digital Applications

This paper presents a novel design and analysis of a low-k source-side asymmetrical spacer halo-doped nanowire MOSFET. The utilization of high-k spacer materials in MOSFETs enhances electrostatic control and minimizes short-channel effects in nanoscale devices. However, the performance of dynamic circuits suffers, with higher fringe capacitance brought on by high-k spacers. Our method focuses on reducing gate capacitance by promising utilization of high-k spacer material. The proposed device is constructed in Silvaco TCAD software, and results show that the low-k source-side asymmetrical spacer halo-doped nanowire MOSFET design exhibits noticeably lower gate capacitance and intrinsic delay, with values of \(1.23\user2{ } \times \user2{ }10^{-17}\) $1.23\times {10}^{-17}$ F and \(1.11\user2{ } \times \user2{ }10^{-12}\) $1.11\times {10}^{-12}$ s, respectively. The CMOS inverter delay and three-stage ring oscillator operating frequency for the proposed device are \(1.82\user2{ } \times \user2{ }10^{-12}\) $1.82\times {10}^{-12}$ s and 91.61 GHz, respectively. The proposed device demonstrates better performance than other spacer engineering devices, making it a strong candidate for digital applications.