Proposal and Analysis of a High Read and Write Noise Margin 6T-SRAM Cell Using Novel Core Insulator Double-Gate (CIDG) MOSFETs

Static random-access memory (SRAM) is in great demand due to the development of portable electronics and its growing popularity in system-on-chip and advanced very-large-scale-integration (VLSI) of integrated circuits. Given the fact that memory takes up to 70% of total chip area, SRAM cell optimization has become a focus of research. In this work, a six-transistor SRAM (6T-SRAM) cell is designed using core insulator double-gate (CIDG) MOSFETs due to their reduced short-channel effects (SCEs). We showed in our previous work that the CIDG MOSFETs provide better digital performance than DG MOSFETs and are negligibly affected by quantum effects. In nanoscale MOSFET technologies, the continual scaling of the supply voltage (V_DD) and dimensions of transistors adversely affects the stability of SRAM cells, i.e., read noise margin (RNM) and write noise margin (WNM). The 6T-SRAM cell designed using CIDG MOSFETs improves the WNM by 3.478% and 2.1837% for cell ratio (CR) and pull-up ratio (PR) equal to 0.7, respectively, as compared to a conventional DG 6T-SRAM cell. Further, its RNM and WNM have been found to be superior as compared to a DG MOSFET SRAM by 6.19% and 3.99%, respectively, for equally sized transistors, i.e., CR and PR equal to 1. The CIDG SRAM cell occupies approximately 4 times lower layout area as compared to TSMC’s 20-nm high-density SRAM cell. The findings of present study confirm that CIDG SRAM cells can be used in applications requiring higher stability and density. The proposed SRAM utilizing a CIDG can be integrated into a radio-frequency (RF) transceiver circuit for an industrial wireless system.