Compact Model for a Negative Capacitance-Based Top-Gated Carbon-Nanotube Field-Effect Transistor

This paper proposes a compact model for a top-gated negative capacitance-based carbon nanotube field-effect transistor (NC-CNTFET). The proposed model relies on a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) configuration. A charge-based modelling approach is used for the top-gated CNTFET, where the surface charge of the CNT is calculated from chirality and gate bias. This charge is the same as the NC-CNTFET device's total charge, based on which the compact model for the proposed device is developed. The ferroelectric material of choice is hafnium silicon oxide (HfSiO). A comparison of the NC-CNTFET with the top-gated CNTFET (TG-CNTFET) is also shown. The results show an improved subthreshold slope and ON/OFF-current ratio in the NC-CNTFET because of the negative capacitance effect of the ferroelectric layer. The impact of different ferroelectric thicknesses is also shown, which suggests further improvement in device performance as the ferroelectric thickness increases.