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<p>Lightweight spiking circuits are the hardware candidate for spike-based neuromorphic computing. This paper presents a lightweight CMOS-based LIF circuit and demonstrates its spiking activity and regulatory mechanisms. The LIF circuit involves only two P-MOS and three N-MOS devices, whose core functions are to implement integration, threshold detection, discharge, and reset. A mathematical model between the input current and output voltage is derived. Then, the functional characteristic between the spiking frequency and the input current intensity is analyzed. Cadence Virtuoso-based circuit simulations show that the circuit can accurately realize the dynamical behavior of the core functions. In addition, the LIF circuit demonstrates good robustness against temperature and process variations. The simulations also show that the total area of the LIF circuit is approximately <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(13.77\mu \textrm{m}^2\)</EquationSource> </InlineEquation> and the energy consumption is approximately 0.096&#xa0;pJ/spike under <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\({130}\,\textrm{nm}\)</EquationSource> </InlineEquation> CMOS process. The LIF circuit can provide a potential approach to implementing compact and low-power spiking circuits in large-scale neuromorphic computing.</p>

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A lightweight CMOS-based LIF circuit: modeling and spiking regulation

  • 期刊论文

  • 发表日期：

    2026年7月11日

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  • Quan Xu,
  • Yixuan Wang,
  • Changfeng Li,
  • Ning Wang,
  • Mo Chen,
  • Xiaoyue Li,
  • Huagan Wu

摘要

Lightweight spiking circuits are the hardware candidate for spike-based neuromorphic computing. This paper presents a lightweight CMOS-based LIF circuit and demonstrates its spiking activity and regulatory mechanisms. The LIF circuit involves only two P-MOS and three N-MOS devices, whose core functions are to implement integration, threshold detection, discharge, and reset. A mathematical model between the input current and output voltage is derived. Then, the functional characteristic between the spiking frequency and the input current intensity is analyzed. Cadence Virtuoso-based circuit simulations show that the circuit can accurately realize the dynamical behavior of the core functions. In addition, the LIF circuit demonstrates good robustness against temperature and process variations. The simulations also show that the total area of the LIF circuit is approximately \(13.77\mu \textrm{m}^2\) and the energy consumption is approximately 0.096 pJ/spike under \({130}\,\textrm{nm}\) CMOS process. The LIF circuit can provide a potential approach to implementing compact and low-power spiking circuits in large-scale neuromorphic computing.