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<p>The paper presents a hardware-efficient image dehazing algorithm and its very large scale integration (VLSI) architecture. The algorithm computes the dark channel on a pixel-to-pixel basis, increases the robustness of atmospheric light estimation using a hardware-friendly local atmospheric light estimation module, and computes the transmission map using a hardware-efficient depth-based transmission map estimation technique. Compared to previous sophisticated dehazing approaches, this study exhibits competitive performance in the quality of the dehazed images. The best of the existing dehazing architectures as well as the proposed architecture are described in Verilog hardware description language (HDL), functionally verified using the Vivado 2019.1 simulator, and synthesized for TSMC 90&#xa0;nm standard cell library by Cadence Genus Synthesis Solution. The results of the implementation show that the suggested design is hardware-efficient and offers higher throughput. The suggested dehazing architecture has the lowest cell count, highest maximum operating frequency, and highest area efficiency compared to the most recent methods and is appropriate for applications with hardware restrictions. The maximum operating frequency and the area efficiency of the proposed dehazing algorithm are 3.78&#xa0;GHz and 513.99&#xa0;Kpixels/s/Gate respectively.</p>

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Hardware-efficient algorithm and architecture for depth-based image dehazing systems

  • 期刊论文

  • 发表日期：

    2025年10月18日

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  • Anuja George

摘要

The paper presents a hardware-efficient image dehazing algorithm and its very large scale integration (VLSI) architecture. The algorithm computes the dark channel on a pixel-to-pixel basis, increases the robustness of atmospheric light estimation using a hardware-friendly local atmospheric light estimation module, and computes the transmission map using a hardware-efficient depth-based transmission map estimation technique. Compared to previous sophisticated dehazing approaches, this study exhibits competitive performance in the quality of the dehazed images. The best of the existing dehazing architectures as well as the proposed architecture are described in Verilog hardware description language (HDL), functionally verified using the Vivado 2019.1 simulator, and synthesized for TSMC 90 nm standard cell library by Cadence Genus Synthesis Solution. The results of the implementation show that the suggested design is hardware-efficient and offers higher throughput. The suggested dehazing architecture has the lowest cell count, highest maximum operating frequency, and highest area efficiency compared to the most recent methods and is appropriate for applications with hardware restrictions. The maximum operating frequency and the area efficiency of the proposed dehazing algorithm are 3.78 GHz and 513.99 Kpixels/s/Gate respectively.