<p>The demand for video in recent years has skyrocketed due to the massive usage of streaming providers, remote work, etc. Thus, efficient measures to comply with this scenario are necessary. The Versatile Video Coding (VVC) is the state-of-the-art standard for video coding, developed to deliver high-quality video with excellent compression capabilities. Nevertheless, the high coding efficiency comes at the cost of a considerable complexity increase. Hence, the traditional solution to this burdensome issue is to design hardware accelerators for the bottleneck steps. In recent video coding formats, the so-called Residual Coding tends to generate most of the data (called Syntax Elements—SEs) that will compose the input of the entropy coding step (the last stage of the process) and, thus, the final coded bitstream. Therefore, one may find it important to speed up the residual data processing to avoid idleness in the video coding flow, which, in turn, may hinder video encoding real-time capabilities. With that in mind, this work proposes an architectural exploration of the VVC Residual SEs (RSEs) for both Transform-based and Transform-skip modes, based on statistical analysis that corroborates the RSEs’ importance for the VVC coding. Finally, a complete and efficient hardware accelerator, able to generate the RSEs in both Transform-based and Transform-skip modes, is introduced, fully compliant with the VVC standard and capable of producing enough data to avoid idleness in the VVC entropy encoder with fewer resources when compared to analogous designs from the literature.</p>