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<p>The Embedded Block Coding with Optimal Truncation (EBCOT) Tier-1 process is a critical component of the Joint Photographic Experts Group 2000 (JPEG2000) framework, significantly influencing throughput in hardware encoders. This paper presents an optimized hardware architecture for a high-performance EBCOT Tier-1 encoder, based on parallel code-block processing. The design features simultaneous bit-plane coding via three parallel channels, along with concurrent arithmetic coding enabled by six context-generating units. To overcome the throughput bottleneck of conventional designs, we introduce a novel multiplexing strategy for the Multiple Quantization coder. Our encoder achieves a throughput of 2782 Mb/s, a 7.3 times improvement over existing implementations, making it well-suited for high-speed JPEG2000 applications. The proposed architecture, when applied to the JPEG2000 encoding system, significantly enhances the circuit performance of the overall encoder on both Field Programmable Gate Array and Application Specific Integrated Circuit platforms. This provides a novel approach to architecture optimization. When processing 512 <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="11554_2024_1612_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">\(\times \)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> 512 size grayscale map, the processing speed can reach more than 160 Frames Per Second, which can well meet the real-time requirements of edge device applications.</p>

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High throughput VLSI design for real-time JPEG 2000 embedded block coding

  • 期刊论文

  • 发表日期：

    2025年1月3日

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  • Xin Jin,
  • Peng Jing,
  • Lin Wang,
  • Yuzhou Dai,
  • Siyuan He,
  • Zhao Ma,
  • Wei Zhang

摘要

The Embedded Block Coding with Optimal Truncation (EBCOT) Tier-1 process is a critical component of the Joint Photographic Experts Group 2000 (JPEG2000) framework, significantly influencing throughput in hardware encoders. This paper presents an optimized hardware architecture for a high-performance EBCOT Tier-1 encoder, based on parallel code-block processing. The design features simultaneous bit-plane coding via three parallel channels, along with concurrent arithmetic coding enabled by six context-generating units. To overcome the throughput bottleneck of conventional designs, we introduce a novel multiplexing strategy for the Multiple Quantization coder. Our encoder achieves a throughput of 2782 Mb/s, a 7.3 times improvement over existing implementations, making it well-suited for high-speed JPEG2000 applications. The proposed architecture, when applied to the JPEG2000 encoding system, significantly enhances the circuit performance of the overall encoder on both Field Programmable Gate Array and Application Specific Integrated Circuit platforms. This provides a novel approach to architecture optimization. When processing 512 \(\times \) × 512 size grayscale map, the processing speed can reach more than 160 Frames Per Second, which can well meet the real-time requirements of edge device applications.