Hardware implementation of iterative method for enhanced affine motion estimation in Versatile video coding

Versatile Video Coding (VVC), the latest advancement in video coding standards, significantly outperforms its predecessor, High Efficiency Video Coding (HEVC), in terms of coding efficiency. Traditional motion representation methods, which rely solely on translational motion, often fall short in accurately depicting object positions in high-definition (HD) video content. The computation of motion with high software complexity can be very time-consuming; therefore, it is essential to utilize a hardware parallel pipeline for efficient processing. This paper introduces a novel, high-throughput iterative method optimized for hardware implementation, which significantly enhances affine motion prediction efficiency within VVC. The hardware architecture employs highly parallel pipeline operations to design matching criteria for computing the optimal combination of affine motion vectors, using 64 \(\times\) $\times$ 64 processing units to support 64 \(\times\) $\times$ 64 to 128 \(\times\) $\times$ 128 coding units. Additionally, a high-efficiency affine iterative array was designed to adjust the motion vectors, along with an edge detection operator to streamline the computation of image gradients. Experimental results demonstrate that the hardware-based approach efficiently processes 4K video at a minimum of 60 frames per second, achieving up to three times the benchmark frame rate. This performance is achieved by leveraging hardware parallelism to meet stringent real-time video encoding standards without compromising coding efficiency.