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<p>For the next-generation NAND flash technology, the enhanced memory window (MW) and decreased operation voltage (OV) are of great importance. Benefiting from the process compatibility and structure similarity, Hf-based ferroelectric field-effect transistors (FeFETs) have garnered significant attention. In this work, the Hf-based ferroelectric gate stacks are fabricated with metal-insulator-ferroelectric-insertlayer-ferroelectric-insulator-silicon (MIFIFIS) structures via inserting Al<sub>2</sub>O<sub>3</sub> &amp; TiO<sub>2</sub> films. Through the co-optimization of structure design, processing conditions, and operating schemes, the MIFIFIS gate stack achieves the MW of 4.15 V (OV of ±9.0 V and pulse width of 10 ms), which can be opened with a low voltage of ±5.0 V. Moreover, the enhanced performances, including leakage and reliability, can be understood by the re-distribution of oxygen vacancy defects and the addition of the tunneling electric field. Our findings may provide for developing high operating speed, storage density, and energy-efficient NAND flash technology based on Hf-based ferroelectric gate stacks.</p>

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Co-optimization of ferroelectric gate stacks on operation voltage and memory window for next-generation NAND flash

  • 期刊论文

  • 发表日期：

    2025年5月21日

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  • Bo Chen,
  • Yizhi Liu,
  • Yifan Wu,
  • Pengpeng Sang,
  • Jixuan Wu,
  • Xuepeng Zhan,
  • Jiezhi Chen

摘要

For the next-generation NAND flash technology, the enhanced memory window (MW) and decreased operation voltage (OV) are of great importance. Benefiting from the process compatibility and structure similarity, Hf-based ferroelectric field-effect transistors (FeFETs) have garnered significant attention. In this work, the Hf-based ferroelectric gate stacks are fabricated with metal-insulator-ferroelectric-insertlayer-ferroelectric-insulator-silicon (MIFIFIS) structures via inserting Al2O3 & TiO2 films. Through the co-optimization of structure design, processing conditions, and operating schemes, the MIFIFIS gate stack achieves the MW of 4.15 V (OV of ±9.0 V and pulse width of 10 ms), which can be opened with a low voltage of ±5.0 V. Moreover, the enhanced performances, including leakage and reliability, can be understood by the re-distribution of oxygen vacancy defects and the addition of the tunneling electric field. Our findings may provide for developing high operating speed, storage density, and energy-efficient NAND flash technology based on Hf-based ferroelectric gate stacks.