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<p>We have investigated the feasibility of array-level operations of FeFET in AND configuration. FeFET devices as well as AND-type arrays have been fabricated and systematically characterized. The disturb-free operations are verified by measurement on both a single cell and an AND-type array. Moreover, optimum read <i>V</i><sub>g</sub> is determined according to the trade-off between D2D variation and <i>I</i><sub>on</sub>/<i>I</i><sub>off</sub> ratio. Such trade-off is even more essential for devices with small size in advanced technology nodes, since the larger variation is induced by a limited number of grains in ferroelectric HfO<sub>2</sub> as indicated by the simulation results. Finally, robust write and read operations of a 1-kbit AND-type FeFET array are experimentally demonstrated.</p>

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An AND-type 1T-FeFET array with robust write and read operations

  • 期刊论文

  • 发表日期：

    2025年1月15日

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  • Jiacheng Xu,
  • Jiayi Zhao,
  • Hongrui Zhang,
  • Haoji Qian,
  • Jiani Gu,
  • Bowen Chen,
  • Gaobo Lin,
  • Rongzong Shen,
  • Xinda Song,
  • Huan Liu,
  • Yian Ding,
  • Minglei Ma,
  • Miaomiao Zhang,
  • Xiao Yu,
  • Bing Chen,
  • Ran Cheng,
  • Gaobo Xu,
  • Huaxiang Yin,
  • Yan Liu,
  • Jiajia Chen,
  • Chengji Jin,
  • Genquan Han

摘要

We have investigated the feasibility of array-level operations of FeFET in AND configuration. FeFET devices as well as AND-type arrays have been fabricated and systematically characterized. The disturb-free operations are verified by measurement on both a single cell and an AND-type array. Moreover, optimum read Vg is determined according to the trade-off between D2D variation and Ion/Ioff ratio. Such trade-off is even more essential for devices with small size in advanced technology nodes, since the larger variation is induced by a limited number of grains in ferroelectric HfO2 as indicated by the simulation results. Finally, robust write and read operations of a 1-kbit AND-type FeFET array are experimentally demonstrated.