A high consistency ramp circuit design method for negative feedback adaptive adjustment mechanism applied to large area array CMOS image sensors
摘要
In this study, a design method of high consistency adaptive ramp circuit based on distributed integration is proposed. The method is applied to a CMOS image sensor with 8192(H)×8192(V) pixel array using 55 nm 1P4M process. The pixel size is 10×10 µm2, the chip area is 88(H)×89(V) mm2, and the analog-to-digital converter is a 12 bit-SS ADC. The experimental results show that the column fixed pattern noise can be reduced to 0.000037% at a frame rate of 10 fps, the inconsistency error among the ramp signals of each column is less than 0.4% LSB, and the chip area and power consumption are only increased by 0.6% and 0.5%, respectively. This method provides a theoretical guidance for the development of high-performance large area array CMOS image sensor.